GaN Power Package Layout for Ringing and Current Balance
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Solution Overview
Problem
GaN transistors in power semiconductors experience high-speed switching, leading to noise generation due to ringing, which degrades signal quality and poses reliability risks due to current concentration and heat generation, while existing solutions fail to effectively suppress noise and ensure uniform current flow.
Innovation Solution
A semiconductor device configuration integrating GaN and MOS transistors with a capacitor in a package, utilizing parallel connections and optimized wiring to separate high-frequency and direct-current paths, reducing loop inductance and suppressing noise, while ensuring uniform current distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If GaN transistors perform high-speed switching, then switching speed is improved, but noise generation increases due to ringing
Solution Approach 1:
The patent segments the current path into distinct high-frequency and direct-current paths. The high-frequency current path is optimized separately from the direct-current path, allowing independent optimization of each path's characteristics to suppress ringing while maintaining high-speed switching performance.
Solution Approach 2:
The patent introduces an intermediary structure (optimized wiring layout and path separation) between the GaN transistor and other circuit elements to reduce loop inductance. This intermediary configuration acts as a mediator that suppresses noise generation without affecting the high-speed switching capability.
2Device complexity
If conventional transistor configurations are used, then device simplicity is maintained, but current concentration and heat generation occur
Solution Approach 1:
The patent applies local quality optimization by creating specific wiring configurations in different regions of the device. The high-frequency path and direct-current path are given different structural characteristics optimized for their respective current types, ensuring uniform current distribution while maintaining overall configuration simplicity.
3Device complexity
If loop inductance is not minimized, then wiring simplicity is maintained, but noise suppression is insufficient
Solution Approach 1:
The wiring is segmented into distinct high-frequency and direct-current paths with optimized geometries. This segmentation allows each path to have minimized loop inductance tailored to its specific current characteristics, achieving noise suppression without excessive overall wiring complexity.
Data Source
AI summary
According to one embodiment, a semiconductor device includes: first, second, and third lead frames; a first transistor which is GaN transistor provided on the first lead frame and electrically connected to the first lead frame; a second transistor which is GaN transistor provided on the second lead frame and electrically connected to the third lead frame; a third transistor which is MOS transistor provided on the third lead frame and electrically connected to the third lead frame and the first transistor; a fourth transistor which is MOS transistor provided on the second lead frame and electrically connected to the second lead frame and the second transistor; and a capacitor electrically connected to the first and the second lead frame; wherein the first, the third, the second, and the fourth transistor are arranged side by side in this order in a first direction.