GaN Device Packaging with Ceramic Substrate and Edge Traces
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Solution Overview
Problem
High voltage semiconductor dies generate significant heat due to high voltages and fast switching speeds, posing challenges in thermal management and electrical connectivity in existing semiconductor packages.
Innovation Solution
The semiconductor packages incorporate a rigid substrate with traces on both sides, electrically and thermally connected through edges, and a molding compound encapsulating the substrate and edges, which includes a high voltage die mechanically and electrically coupled to the substrate using clips or wire bonds, and copper pillars for enhanced thermal and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If traditional PCB designs are used for high voltage die, then electrical connectivity is achieved, but thermal dissipation is insufficient due to significant heat generation from high voltages and fast switching speeds
Solution Approach 1:
The patent employs a composite substrate structure combining ceramic material with copper layers. The ceramic provides excellent thermal conductivity for heat dissipation while the copper layers provide electrical connectivity. This composite approach resolves the contradiction by simultaneously achieving both thermal management and electrical functionality that traditional single-material PCB designs cannot provide.
Solution Approach 2:
The patent introduces an intermediary ceramic substrate between the high voltage die and the external environment. This ceramic substrate acts as a thermal mediator that conducts heat away from the die while maintaining electrical isolation and connectivity through its integrated copper trace system, thus improving thermal dissipation without compromising electrical reliability.
2Temperature
If larger packages are used to accommodate thermal management components, then thermal dissipation improves, but package size increases
Solution Approach 1:
The patent merges the substrate, thermal management system, and electrical interconnect structure into a single integrated ceramic component. The copper traces are embedded within the ceramic substrate itself, eliminating the need for separate external thermal management components and reducing overall package size while maintaining effective heat dissipation.
Solution Approach 2:
The patent utilizes the vertical dimension by creating multi-layer copper traces within the ceramic substrate thickness. Heat is dissipated through the thickness of the ceramic substrate to external heat sinks, while electrical connections are established through vertically stacked copper layers, effectively using three-dimensional space to achieve both thermal and electrical functions without increasing the horizontal package footprint.
3Reliability
If more traces are added to provide electrical connectivity between sides of substrate, then electrical connectivity improves, but device complexity increases
Solution Approach 1:
The patent segments the electrical interconnection function across multiple copper layers within the ceramic substrate. Instead of adding complex surface traces, the connectivity is achieved through stacked copper layers connected via vertical vias, dividing the interconnection task into manageable layers and reducing surface complexity while maintaining robust electrical connectivity between substrate sides.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration provides effective thermal dissipation and electrical connectivity, reducing package size and improving reliability while maintaining electrical isolation, as demonstrated by simulations showing temperature reductions in ceramic multi-chip modules compared to traditional PCB designs.
Implementation Method 1
High voltage die are known to produce large amounts of heat due to large voltages and fast switching speeds
Implementation Method 2
a molding compound encapsulating at least the first and the one or more edges of the substrate
Implementation Method 3
The die can be electrically coupled through clips and wirebonds to power and signal
Data Source
AI summary
Implementations of semiconductor packages may include: a substrate having one or more traces on a first side and one or more traces on a second side of the substrate. The substrate may be rigid. The packages may include at least one die mechanically and electrically coupled to the first side of the substrate. The die may be a high voltage die. The package may include one or more traces along one or more edges of the substrate. The one or more traces along the one or more edges of the substrate provide electrical connectivity between the one or more traces on the first side of the substrate and the one or more traces on the second side of the substrate. The package may also include a molding compound encapsulating at least the first and the one or more edges of the ceramic substrate.