GaN PMOS Interface Structure for 2DEG Suppression
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Solution Overview
Problem
GaN power semiconductor devices face issues with parasitic inductance and electromagnetic interference (EMI) due to fast switching speeds, and traditional PMOS integration is limited by two-dimensional electron gas (2DEG) suppression, leading to electron flow and suppressed current characteristics.
Innovation Solution
The power semiconductor device features a rough or capture interface on the epitaxial layer to disrupt or trap 2DEG, using ion bombardment or implantation to form a non-flat or doped surface, reducing polarization electron flow and enhancing PMOS performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If GaN power semiconductor devices operate at fast switching speeds, then high-frequency performance is improved, but parasitic inductance and electromagnetic interference increase causing over-voltage and EMI issues
Solution Approach 1:
The patent merges the GaN power semiconductor device with the driver circuit into a single integrated device structure, where the GaN device serves as both the power switch and the driver output stage. This integration eliminates the external connection parasitic inductance between separate components, allowing fast switching speeds to be maintained without the EMI and over-voltage problems caused by parasitic inductance in conventional separate-component designs.
2Device complexity
If traditional GaN PMOS utilizes AlGaN/GaN polarization to form 2DEG and 2DHG for achieving hole channel, then device structure is simplified, but electron flow suppresses the current characteristics of PMOS
Solution Approach 1:
The patent extracts and removes the two-dimensional electron gas (2DEG) layer from the device structure through selective etching processes. By removing this harmful electron layer that causes unwanted electron flow and suppresses PMOS current characteristics, the device achieves reliable hole-channel operation while maintaining a relatively simple overall structure.
Solution Approach 2:
The patent applies different material compositions and structures to different regions of the device. The channel region uses specific AlGaN/GaN heterostructure configurations optimized for hole transport, while other regions use different compositions to prevent 2DEG formation. This local optimization ensures that the device structure supports reliable PMOS operation without requiring complete structural redesign.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses 2DEG, improving PMOS current characteristics and transitioning to enhanced-mode operation, reducing EMI and parasitic inductance effects.
Implementation Method 1
The rough interface is used to disrupt the atomic structure of the top surface, thereby breaking down the two-dimensional electron gas
Implementation Method 2
The ions doped in the capture interface are used to trap the two-dimensional electron gas
Data Source
AI summary
A power semiconductor device includes a substrate, an epitaxial layer, a barrier layer, a channel layer, a source pin and a drain pin, and a gate structure. The epitaxial layer is over the substrate and has a top surface that is a rough interface or a capture interface doped with ions. The rough interface is used to disrupt the atomic structure of the top surface, thereby breaking down the two-dimensional electron gas. The ions doped in the capture interface are used to trap the two-dimensional electron gas. The barrier layer is in contact with the top surface of the epitaxial layer. The channel layer is disposed on the barrier layer. The source pin and the drain pin are respectively disposed on two sides of the channel layer. The gate pin is disposed over the channel layer.