GaN Power Device Defect-Tolerant Layout and Packaging
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Solution Overview
Problem
Gallium nitride (GaN)-based power devices face challenges in controlling material defects, leading to low yield and increased production costs, particularly for large die sizes where the probability of defects is high, affecting the performance and efficiency of power converters.
Innovation Solution
The solution involves dividing GaN power switching device dies into smaller sub-devices, identifying and selectively connecting only functional sub-devices in a parallel arrangement during packaging, using techniques like wire bonding or metal bumping, to exclude defective sub-devices and increase yield, particularly suitable for lateral power devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If large die size is used for high power devices, then power rating is improved, but yield deteriorates due to high probability of defects
Solution Approach 1:
The patent divides a large power device die into multiple smaller sub-devices (e.g., multiple HEMT devices) that can be independently tested and selectively connected. This segmentation allows the large die to achieve high power ratings through parallel connection of functional sub-devices while tolerating defective regions, thereby resolving the contradiction between high power rating and low yield caused by defects in large area devices.
2Reliability
If multiple small dies are used for co-packaging, then yield is improved, but device complexity increases due to bonding many small dies
Solution Approach 1:
The patent merges multiple small sub-devices into a single integrated die structure with shared substrate and common packaging infrastructure. This merging approach maintains the yield benefits of using multiple small functional units while reducing bonding complexity by consolidating interconnections and packaging requirements compared to treating them as separate co-packaged devices.
3Ease of manufacture
If conventional silicon-based devices are used with substrate as drain, then manufacturing is simplified, but defective dies cannot be retained in co-package due to high voltage bias risks
Solution Approach 1:
The patent applies local quality by implementing different voltage potential configurations in different regions of the device. Specifically, it uses lateral power device structures where the substrate is not biased at high voltage, allowing defective sub-devices to be isolated and excluded from high voltage operation while retaining functional sub-devices in the co-package. This local differentiation resolves the contradiction between manufacturing simplicity and performance safety.
Data Source
AI summary
Use of gallium nitride (GaN) semiconductor material for power devices is challenging due to low yield caused by high defect density on the wafer. Device layout on the wafer, chip probing, and device packaging increase the yield of large area power devices. Device dies containing a plurality of lower-power sub-devices are used to achieve high power ratings, by connecting only functional sub-devices together in the package, while being tolerant of defective sub-devices by selectively excluding the defective sub-devices. The packages and methods are particularly relevant to GaN power switching devices such as high electron mobility transistors (GaN HEMT).