Low Inductance GaN Power Module Terminal Design
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Solution Overview
Problem
Current power modules for high-current applications, particularly those using GaN HEMTs, face challenges with high parasitic inductance in both gate drive and power commutation loops, limiting their performance due to design constraints that prioritize creepage and clearance requirements over reduced stray inductance.
Innovation Solution
The development of power modules with a housing configuration that includes power terminals at a first height to meet creepage and clearance specifications, and low-profile control terminals and dynamic performance terminals at a second height to minimize inductance in the gate drive and power commutation loops, allowing for reduced parasitic inductance and improved performance at higher switching frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power terminals are positioned at standard height to meet creepage and clearance requirements, then electrical safety is improved, but parasitic inductance in the power loop increases
Solution Approach 1:
The patent positions power terminals at different heights (first height for power terminals, second height for control terminals) to create a three-dimensional terminal arrangement. This dimensional differentiation allows power terminals to maintain standard creepage and clearance distances while control terminals are lowered to reduce gate loop inductance, effectively resolving the contradiction between electrical safety and parasitic inductance reduction
2Object-generated harmful factors
If control terminals are lowered to reduce gate loop inductance, then switching performance is improved, but creepage and clearance requirements may be compromised
Solution Approach 1:
The patent segments the terminal structure into two distinct height levels: power terminals at a first height and control terminals at a second height. This segmentation allows each terminal type to be optimized independently - power terminals maintain standard height for creepage and clearance compliance, while control terminals are lowered to minimize gate loop inductance, thereby resolving the contradiction between switching performance and safety requirements
3Reliability
If standard housing height is used to meet creepage requirements, then electrical isolation is improved, but power loop inductance increases
Solution Approach 1:
The patent introduces vertical dimension differentiation by positioning power terminals at a first height and control terminals at a second height. This allows the housing to maintain standard overall height for creepage and clearance compliance while creating optimized current paths through selective terminal positioning, thereby reducing power loop inductance without compromising electrical isolation
Data Source
AI summary
Low inductance power modules for ultra-fast wide-bandgap semiconductor power switching devices are disclosed. Conductive tracks define power buses for a switching topology, e.g. comprising GaN E-HEMTs, with power terminals extending from the power buses through the housing to provide a heatsink-to-busbar distance which meets creepage and clearance requirements. Low-profile, low-inductance terminals for gate and source-sense connections extend from contact areas located adjacent each power switching device to provide for a low inductance gate drive loop, for high di/dt switching. The gate driver board is mounted on the low-profile terminals, inside or outside of the housing, with decoupling capacitors provided on the driver board. For paralleled switches, additional terminals, which are referred to as dynamic performance pins, are provided to the power buses. These pins are configured to provide a low inductance path for high-frequency current and balance inductances of the power commutation loops for each switch.