GaN RF DAC Architecture for Direct Digital Antenna Synthesis

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Solution Overview

Problem

Conventional circuits using CMOS fabrication techniques cannot synthesize digital waveforms directly at an antenna for high RF power levels, requiring separate circuits for signal waveform generation and RF power amplification, and are susceptible to high voltage standing wave ratios due to operating voltage differences.

Innovation Solution

A high power digital-to-analog converter comprising an array of transistors in a binary sequence, a depletion mode FET, and an array of switches that selectively activate transistors to provide binary weighted collector currents, eliminating the need for an RF signal generator and power amplifier chain by directly synthesizing a digital waveform at an antenna, using a composite device combining gallium nitride and silicon germanium transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate circuits are used for signal waveform generation and RF power amplification, then transistors are protected from high voltage breakdown, but device complexity increases and transmitter size increases

Engineering Contradiction:
Improvetransistor protection from high voltage breakdownVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the digital waveform generation circuit and RF power amplification circuit into a single integrated device. The digital-to-analog converter directly drives the power amplifier stage, eliminating the need for separate RF signal generator and power amplifier circuits. This integration reduces device complexity while maintaining transistor protection through proper circuit design.

Inventive Principle:
Principle #5Merging (Combining)

2Ease of manufacture

If conventional CMOS circuits are used, then manufacturing is easier, but direct digital waveform synthesis at antenna for high RF power levels is not possible

Engineering Contradiction:
Improvemanufacturing easeVSAvoiddirect digital waveform synthesis capability
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent employs a composite device structure that integrates digital-to-analog converter circuits with high-power RF amplifier circuits. This composite approach combines the manufacturing advantages of conventional CMOS fabrication with the high-power capabilities of specialized RF transistor designs, enabling direct digital waveform synthesis at the antenna while maintaining ease of manufacture through standardized fabrication processes.

Inventive Principle:
Principle #40Composite materials

3Productivity

If entire RF signal generation and power amplification chain is eliminated, then transmitter size is reduced and efficiency is improved, but conventional circuits cannot achieve this

Engineering Contradiction:
Improvetransmitter efficiencyVSAvoidcircuit integration complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the digital waveform generation and RF power amplification functions into a single integrated digital-to-analog converter device. This eliminates the need for separate RF signal generators and power amplifiers, reducing transmitter size and improving efficiency. The integration is achieved through careful circuit design that allows direct driving of the power amplifier stage by the digital-to-analog converter.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS7903016B1High power and high frequency gallium nitride based digital to analog converter for direct digital radio frequency power waveform synthesis
Publication Date: 2011.03.08 HARRIS CORP
  • US7903016B1 patent drawing
  • US7903016B1 patent drawing
  • US7903016B1 patent drawing

AI summary

A high power digital to analog converter (DAC) includes (a) an array of n bipolar transistors arranged in a binary sequence, (b) a depletion mode FET and (c) an array of n switches. The collector terminals of each bipolar transistor in the array are tied together. Furthermore, the depletion mode FET includes a source terminal which is directly connected to the collector terminals of each bipolar transistor. The FET also includes a gate terminal connected to a ground potential, and a drain terminal. Each bipolar transistor is sized to be a factor larger than its preceding transistor in the array of n bipolar transistors, for example, twice as large. The array of n switches is controlled by a digital word of n bits. Each of the n switches selectively activates a respective bipolar transistor in the array of n bipolar transistors. As the n switches are selectively activated, the array of n bipolar transistors provides n binary weighted collector currents in the source terminal of the FET. The n collector currents are equal to a sum of the binary weighted collector currents. The drain terminal of the FET provides the same sum of the binary weighted collector currents.