GaN Semiconductor Device Epitaxial Impurity Integration
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Solution Overview
Problem
It is challenging to form GaN based semiconductor elements, such as transistors and diodes, with different impurity layer structures on a single chip due to low activation rates of impurities introduced by ion implantation, which hinders the scaling-down of systems and increases power consumption.
Innovation Solution
A semiconductor device configuration and manufacturing method involving epitaxial growth of GaN based semiconductor layers with varying impurity concentrations, allowing for the formation of transistors and diodes with distinct structures on a single chip, without relying on ion implantation, thereby enhancing integration and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implantation is used to introduce impurities, then impurity layers can be formed, but the activation rate of impurities is low
Solution Approach 1:
The patent extracts and eliminates the ion implantation process from the manufacturing flow. Instead of using ion implantation to introduce impurities, the invention forms impurity layers through in-situ doping during epitaxial growth, completely removing the problematic step that caused low activation rates and manufacturing difficulties.
Solution Approach 2:
The patent replaces the mechanical/physical ion implantation process with a chemical epitaxial growth process. By substituting the mechanical bombardment of ions with a controlled chemical deposition process that incorporates dopants during layer formation, the invention achieves high impurity activation rates while enabling precise control over impurity layer structures.
2Productivity
If multiple GaN based semiconductor elements are formed in one chip, then system scaling-down and low power consumption are achieved, but it becomes difficult to form elements requiring different impurity layer structures
Solution Approach 1:
The patent applies local quality by forming different impurity layer structures in different regions of the same chip through selective epitaxial growth. By controlling doping conditions during specific growth stages and using selective area growth techniques, the invention creates locally optimized impurity layers tailored to the specific requirements of each device type (transistors, diodes, etc.) while maintaining high integration density.
Solution Approach 2:
The patent segments the epitaxial growth process into multiple stages, with each stage forming specific impurity layers with tailored compositions. By dividing the overall device fabrication into sequential growth steps, each optimized for particular device regions, the invention enables multiple element types with different impurity requirements to coexist on a single chip.
3Ease of manufacture
If ion implantation is used, then impurity layers can be formed, but contact resistance increases
Solution Approach 1:
The patent performs preliminary action by incorporating impurities directly into the semiconductor layers during the epitaxial growth process itself, before subsequent processing steps. This in-situ doping ensures that impurities are uniformly distributed and properly activated within the crystal structure from the beginning, eliminating the need for post-growth ion implantation and annealing steps that increase contact resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of transistors and diodes on a single chip, achieving miniaturization and low power consumption while improving on-state current and breakdown voltage, and allowing for the formation of devices with high performance and efficient power management.
Implementation Method 1
a second GaN based semiconductor layer of a first conductive type having an impurity concentration of the first conductive type lower than that of the first GaN based semiconductor layer formed thereon
Data Source
AI summary
A semiconductor device according to an embodiment includes a first GaN based semiconductor layer of a first conductive type, a second GaN based semiconductor layer of the first conductive type provided above the first GaN based semiconductor layer, a third GaN based semiconductor layer of a second conductive type provided above a part of the second GaN based semiconductor layer, a epitaxially grown fourth GaN based semiconductor layer of the first conductive type provided above the third GaN based semiconductor layer, a gate insulating film provided on the second, third, and fourth GaN based semiconductor layer, a gate electrode provided on the gate insulating film, a first electrode provided on the fourth GaN based semiconductor layer, a second electrode provided at the side of the first GaN based semiconductor layer opposite to the second GaN based semiconductor layer, and a third electrode provided on the second GaN based semiconductor layer.