GaN Semiconductor Layer Structure for Pulse Dissipation
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Solution Overview
Problem
GaN-based lateral transistors (HFETs) are prone to damage from inductively driven current pulses due to high power density and inhomogeneous field distribution, as they cannot dissipate pulse energy without damaging the active blocking structure, unlike Si-based power transistors.
Innovation Solution
A semiconductor layer structure with a thick buffer layer and/or ion implantation in the substrate to create a space-charge region, allowing vertical dissipation of overvoltage pulses to the substrate, reducing power density and preventing component damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick buffer layer is used to dissipate voltage pulses vertically, then power density is reduced and component damage is prevented, but the device complexity increases
Solution Approach 1:
The patent introduces a vertical current path through the buffer layer to the substrate, adding a third dimension (vertical direction) for energy dissipation. This complements the existing lateral dissipation path, creating a two-dimensional dissipation network that reduces power density without requiring additional lateral chip area.
Solution Approach 2:
The buffer layer acts as an intermediary structure between the active transistor channel and the substrate. It provides a controlled impedance path that safely dissipates voltage pulses, mediating between the high-voltage stress and the sensitive active structures above and the substrate below.
2Reliability
If ion implantation is used to create a space-charge region, then the drain voltage threshold is determined and pulse dissipation is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses ion implantation to modify the electrical parameters of the substrate, creating a space-charge region with specific doping characteristics. By controlling the ion implantation dose and energy, the drain voltage threshold can be precisely tuned to match the breakdown voltage of the active structure, enabling controlled pulse dissipation.
3Loss of energy
If the buffer layer thickness is increased to reduce power density, then energy dissipation capability is improved, but the area of the stationary object increases
Solution Approach 1:
The patent exploits the vertical dimension by increasing buffer layer thickness to provide additional volume for energy dissipation. This vertical expansion allows the existing chip footprint to handle higher energy pulses, effectively decoupling energy dissipation capability from lateral chip area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure effectively dissipates induced voltage pulses at low power density, enhancing the voltage endurance and preventing damage to the active semiconductor structure without requiring additional chip area.
Implementation Method 1
an ion implantation into the substrate determine(s) a drain voltage threshold
Implementation Method 2
Si-based power transistors, for example, can tolerate such a voltage or current pulse up to a specific energy level or can dissipate the pulse energy (avalanche resistance)
Data Source
AI summary
This invention relates to a semiconductor layer structure. The semiconductor layer structure described includes a substrate and a buffer layer deposited onto the substrate. The semiconductor layer structure is characterized in that a drain voltage threshold lower than the breakdown voltage threshold is determined by isolating ions that are selectively implanted in just one region of the substrate into the substrate, wherein charge can dissipate from the one contact through the buffer layer towards a substrate region without isolating ions, if the one potential deviates from the other at least by the drain voltage threshold, and wherein the substrate region without isolating ions is located underneath the one contact. The semiconductor layer structure described allows dissipation of currents induced by induction in blocking active structures without damaging the active structures.