GaN Semiconductor Device With Localized High Doping Region
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Solution Overview
Problem
It is challenging to increase activation rates in p-type GaN-based semiconductors, leading to higher contact resistance between p-type GaN-based semiconductors and electrodes, which hinders the development of high-withstand voltage and high-integration semiconductor devices.
Innovation Solution
The semiconductor device employs an epitaxial growth technique to form a p-type GaN layer with varying impurity concentrations, creating a low and high impurity concentration region, and a trench structure with a gate insulating film, which enhances the activation rate of p-type impurities and reduces contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If p-type GaN-based semiconductor is used to achieve high breakdown strength and vertical device structure, then withstand voltage and integration are improved, but contact resistance between p-type GaN and electrode increases due to difficult activation rate enhancement
Solution Approach 1:
The patent applies local quality by creating a multi-layer structure where a p-type AlGaN layer with high impurity concentration is positioned between the p-type GaN layer and the electrode. This localized region with different material composition (AlGaN instead of GaN) and higher doping concentration specifically addresses the contact resistance problem at the electrode interface without altering the bulk properties of the p-type GaN layer, thereby maintaining breakdown strength while improving contact characteristics
Solution Approach 2:
The patent employs composite materials by combining p-type GaN with a p-type AlGaN layer having higher impurity concentration. This composite structure leverages the high breakdown strength of p-type GaN while utilizing the superior electrical activation properties of p-type AlGaN at the contact region, achieving both high voltage withstand capability and low contact resistance through material composition optimization
2Reliability
If activation rate in p-type GaN-based semiconductor is increased to reduce contact resistance, then contact resistance decreases, but it remains difficult to achieve high activation rates due to material properties
Solution Approach 1:
The patent introduces a p-type AlGaN layer with high impurity concentration as an intermediary between the p-type GaN layer and the electrode. This intermediate layer serves as a mediator that facilitates better electrical contact by providing a region with higher carrier concentration and improved activation characteristics, bridging the gap between the bulk p-type GaN and the electrode while overcoming the inherent difficulty of achieving high activation rates in p-type GaN
Solution Approach 2:
The patent applies parameter changes by altering the material composition (from GaN to AlGaN) and impurity concentration (increasing doping level) in the contact region. These parameter modifications enable higher activation rates and improved electrical contact properties without compromising the overall device structure and breakdown strength requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in stable operation of MOSFETs with reduced contact resistance and junction leakage current, enabling higher integration and withstand voltage in semiconductor devices.
Implementation Method 1
The semiconductor device employs an epitaxial growth technique to form a p-type GaN layer with varying impurity concentrations
Data Source
AI summary
A semiconductor device according to one embodiment includes an n-type first GaN-based semiconductor layer, a p-type second GaN-based semiconductor layer on the first GaN-based semiconductor layer. The second GaN-based semiconductor layer includes a low impurity concentration region and a high impurity concentration region. An n-type third GaN-based semiconductor layer is provided on the second GaN-based semiconductor layer. The device includes a gate electrode being located adjacent to the third GaN-based semiconductor layer, the low impurity concentration region, and the first GaN-based semiconductor layer intervening a gate insulating film. The device includes a first electrode on the third GaN-based semiconductor layer, a second electrode on the high impurity concentration region, and a third electrode on the opposite side of the first GaN-based semiconductor layer from the second GaN-based semiconductor layer.