GaN-SiC Cascode Clamping Circuit for JFET Gate Overstress

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Solution Overview

Problem

The integration of a low-voltage GaN HEMT with a high-voltage SiC JFET in a cascode configuration faces challenges due to the lack of avalanche capability in GaN HEMT, leading to gate overstress of the SiC JFET during switching processes.

Innovation Solution

A cascode semiconductor device is designed with a normally-on high-voltage SiC JFET, a normally-off low-voltage GaN HEMT, and a clamping circuit. The clamping circuit is connected between the drain and gate of the GaN HEMT, with a clamping voltage that protects the SiC JFET from gate overstress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a cascode configuration integrating GaN HEMT and SiC JFET is used, then switching speed and operation temperature are improved, but gate overstress occurs during switching processes

Engineering Contradiction:

Improveswitching speedVSAvoidgate overstress

Core Design Contradiction:

SpeedVSObject-affected harmful factors

Solution Approach 1:

A clamping circuit is introduced as an intermediary component between the GaN HEMT drain and gate terminals. This clamping circuit actively monitors and limits the voltage difference during switching transitions, preventing excessive voltage spikes from reaching the SiC JFET gate while allowing the GaN HEMT to operate at its full switching speed capability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The clamping circuit is designed with appropriate voltage thresholds that anticipate potential overvoltage conditions before they damage the SiC JFET gate. By establishing voltage clamping levels slightly below the maximum gate voltage rating, the circuit provides a safety margin that cushions against voltage transients during switching operations.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If avalanche capability is added to GaN HEMT, then gate overstress protection is improved, but device complexity increases

Engineering Contradiction:

Improvegate overstress protectionVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The protection function is segmented from the main power switching device. Instead of modifying the GaN HEMT structure to include avalanche capability, the protection function is implemented by a separate clamping circuit with diodes and resistors, allowing each component to be optimized for its specific function.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The clamping circuit serves as an intermediary protection layer that provides avalanche-like protection without requiring the GaN HEMT itself to have avalanche capability. This mediator approach maintains the simplicity of the GaN HEMT while adding protection through external passive components.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The integration of the clamping circuit effectively suppresses drain-source overvoltage of the GaN HEMT during switching, thereby protecting the SiC JFET from gate overstress without compromising the switching performance of the cascode GaN/SiC device.

Implementation Method 1

The clamping circuit is connected between the second drain terminal and the second gate terminal and has a clamping voltage. The clamping voltage is greater than a magnitude of a threshold voltage of the SiC JFET and smaller than a reverse gate voltage limit of the SiC JFET.

Methodology Applied

Scientific EffectClamping voltage effect:

Implementation Method 2

a normally-off low-voltage (LV) gallium nitride (GaN) high-electron-mobility transistor (HEMT)

Methodology Applied

Scientific EffectHigh-electron-mobility transistor conduction:

Implementation Method 3

a normally-on high-voltage (HV) silicon carbide (SiC) junction field-effect transistor (JFET)

Methodology Applied

Scientific EffectJunction field-effect transistor voltage blocking:

Data Source

PatentUS20250120173A1Cascode Semiconductor Devices

Publication Date: 2025.04.10 THE HONG KONG UNIV OF SCI & TECH

AI summary

A cascode semiconductor device comprise a normally-on high-voltage (HV) silicon carbide (SiC) junction field-effect transistor (JFET), a normally-off low-voltage (LV) gallium nitride (GaN) high-electron-mobility transistor (HEMT) and a clamping circuit. The SiC JFET has a first gate terminal, a first drain terminal and a first source terminal. The GaN HEMT has a second gate terminal, a second drain terminal and a second source terminal. The second drain terminal is connected to the first source terminal. The second source terminal is connected to the first gate terminal. The clamping circuit is connected between the second drain terminal and the second gate terminal and has a clamping voltage. The clamping voltage is greater than a magnitude of a threshold voltage of the SiC JFET and smaller than a reverse gate voltage limit of the SiC JFET.