GaN-on-Silicon Microwave IC Layout for Parasitic Isolation
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Solution Overview
Problem
Integrated circuits using gallium nitride on silicon substrates face challenges with parasitic conductive layers that lead to electromagnetic interference and efficiency losses due to parasitic currents, particularly in RF applications.
Innovation Solution
Incorporating insulating materials, such as glass, between active devices to form passive components, which physically interrupts parasitic conductive layers and forms passive components over these insulating materials, reducing electromagnetic interference and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If gallium nitride devices are formed on silicon substrates, then high-power and high-frequency performance is improved, but parasitic conductive layers cause electromagnetic interference and efficiency losses
Solution Approach 1:
The patent segments the silicon substrate into distinct regions: active device regions with gallium nitride layers and passive component regions with insulating materials. This segmentation isolates parasitic conductive layers from passive components, allowing high-power gallium nitride devices to maintain their power amplification capability while preventing parasitic effects from degrading circuit performance
Solution Approach 2:
The patent introduces insulating materials as intermediary layers between active gallium nitride devices and passive components. These intermediary insulating regions act as barriers that block parasitic conductive paths while allowing the gallium nitride devices to continue providing high-power performance. The insulating materials serve as mediators that enable coexistence of high-power active devices and sensitive passive components on the same substrate
2Device complexity
If passive components are formed directly on silicon substrate, then device integration is simplified, but electromagnetic interference from parasitic currents increases
Solution Approach 1:
The patent applies local quality by creating different substrate characteristics in different regions: regions with insulating materials for passive components and regions with silicon substrate for active devices. This local differentiation allows passive components to be formed with reduced electromagnetic interference while maintaining simplified integration overall. The insulating regions are strategically placed only where needed to protect passive components without complicating the overall device structure
3Object-generated harmful factors
If insulating materials are introduced to interrupt parasitic conductive layers, then electromagnetic interference is reduced, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent merges the formation of insulating regions with the existing semiconductor fabrication process flow. Insulating materials are deposited and patterned alongside the gallium nitride layer formation, combining multiple functions into integrated process steps. This merging approach reduces the overall manufacturing complexity despite introducing insulating materials, as the insulating region formation is consolidated with the active device fabrication rather than being a separate additive step
Data Source
AI summary
Various methods of forming integrated circuits formed using gallium nitride and other materials are described. An example method includes forming a first integrated device over a first semiconductor structure in a first region of the integrated circuit, forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit, etching a cavity in a third region of the of the integrated circuit located between the first region and the second region, filling the cavity with an insulating material, and forming a passive component over the insulating material in the third region of the integrated circuit. In other aspects, the method can include grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure and, after the grinding, forming a ground plane over the back side of the semiconductor substrate.