GaN-on-Silicon Interconnect Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
The RF performance of GaN-on-silicon structures is limited by parasitic capacitance between interconnects on the front side of the substrate and the ground plane on the back side, which degrades performance at high frequencies.
Innovation Solution
Replacing at least a portion of the substrate between the interconnects and the ground with a material having a lower dielectric constant than silicon, such as silicon dioxide, formed using a LOCOS process, to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon substrate is used between interconnects and ground plane, then structural integrity is maintained, but parasitic capacitance increases degrading RF performance
Solution Approach 1:
The patent applies local quality by replacing the silicon substrate with silicon dioxide only in the interconnect areas where parasitic capacitance is problematic, while maintaining silicon substrate in device areas for structural integrity. This localized material substitution reduces parasitic capacitance between interconnects and ground plane without compromising overall device performance.
Solution Approach 2:
The patent changes the dielectric parameter of the substrate material from silicon (high dielectric constant) to silicon dioxide (low dielectric constant) in specific regions. This parameter change directly reduces the parasitic capacitance formed between interconnects and the ground plane, thereby improving RF performance at high frequencies.
2Object-affected harmful factors
If LOCOS process is used to form silicon dioxide regions, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The LOCOS process performs preliminary oxidation of silicon to form silicon dioxide regions before subsequent device fabrication steps. By pre-forming the low-dielectric-constant regions in advance, the patent reduces parasitic capacitance early in the manufacturing sequence, and subsequent processing steps can proceed without additional complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reduction in dielectric constant between the interconnects and the ground plane effectively decreases parasitic capacitance, thereby enhancing the RF performance of GaN-on-silicon devices, especially at high frequencies.
Implementation Method 1
Replacing at least a portion of the substrate between the interconnects and the ground with a material having a lower dielectric constant than silicon... the capacitance between the front side interconnects and ground is a function of the dielectric constant of the material between the front side interconnects and ground
Implementation Method 2
oxidizing the silicon substrate in the trenches to form silicon dioxide regions... The silicon dioxide may be formed using a LOCOS (Local Oxidation of Silicon) process
Data Source
AI summary
Semiconductor structures with reduced parasitic capacitance between interconnects and ground, for example, are described. An example method for making a semiconductor structure includes forming a trench in an interconnect area of a substrate between first and second device areas in the semiconductor structure, forming a low dielectric constant material region in the trench, forming a III-nitride material layer over the substrate and over the low dielectric constant material region in the trench, forming a first device in the III-nitride material layer in the first device area, forming a second device in the III-nitride material layer in the second device area, and forming an interconnect over the low dielectric constant material region, the interconnect comprising a continuous conductive metal interconnect from the first device area, over the low dielectric constant material region, and to the second device area.