GaN-on-Silicon Carburization Using a SiC Template Layer
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Solution Overview
Problem
Current semiconductor technologies, such as Si and III-V, face limitations in power delivery and RF communication due to fundamental constraints, necessitating the development of more efficient and compact solutions, which gallium nitride (GaN) integrated circuits aim to address through advanced fabrication and packaging techniques.
Innovation Solution
The integration of GaN transistors on carburized silicon substrates using a thin SiC template to reduce defect density and enable monolithic 3D integration with Si CMOS, allowing for efficient power delivery and RF performance in smaller form factors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If GaN layers are grown directly on silicon substrates, then manufacturing cost is reduced, but defect density increases due to lattice mismatch
Solution Approach 1:
A thin SiC template layer is introduced as an intermediary between the silicon substrate and the GaN layer. This template reduces the lattice mismatch and thermal expansion coefficient difference, thereby reducing defect density while still allowing GaN growth on inexpensive silicon substrates
Solution Approach 2:
The patent modifies the substrate surface properties by creating a SiC template that changes the lattice constant and thermal expansion characteristics, enabling better epitaxial growth of GaN layers and reducing dislocation defects
2Device complexity
If traditional planar integration is used, then manufacturing process is simple, but power delivery efficiency and RF performance are limited
Solution Approach 1:
The patent transitions from planar 2D integration to monolithic 3D integration by stacking multiple functional layers vertically, including GaN power devices, Si CMOS logic, and interconnect layers, enabling superior power delivery efficiency and RF performance through three-dimensional architecture
3Volume of moving object
If device size is reduced for compact form factors, then integration density increases, but parasitic inductance and capacitance increase
Solution Approach 1:
By stacking layers vertically in 3D, the patent reduces the lateral footprint while maintaining electrical performance. The vertical interconnects through the stacked layers minimize parasitic inductance compared to lateral connections, enabling compact form factors without sacrificing power delivery efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-power, high-frequency GaN 3D ICs that are more efficient, compact, and cost-effective than existing technologies, supporting next-generation compute solutions with improved energy efficiency and reduced parasitic inductance and capacitance.
Implementation Method 1
a silicon substrate is provided. The silicon substrate is carburized to form a SiC template
Implementation Method 2
III-N epitaxy is performed on the created pseudo-substrates
Data Source
AI summary
Gallium nitride (GaN) layer on substrate carburization for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon. A layer comprising silicon and carbon is above the substrate. A layer comprising gallium and nitrogen is on the layer comprising silicon and carbon.