GaN Semiconductor Wafer with SiNx Interlayer for Crack Prevention
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Solution Overview
Problem
The challenge is to minimize dislocation defects and wafer bowing/cracking in semiconductor wafers, particularly when using silicon substrates for GaN-based LEDs, due to lattice mismatches and thermal expansion differences, which affect the quality and efficiency of optoelectronic devices.
Innovation Solution
The use of thin SiNx interlayers within the GaN layer, allowing GaN to penetrate and form three-dimensional domains, combined with AIGaN and AlN layers for stress management and lattice matching, to reduce threading dislocations and prevent cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick layer of GaN is grown to reduce dislocation density, then threading dislocations are reduced, but wafer curvature and cracking increase due to lattice mismatch and thermal expansion differences
Solution Approach 1:
A thin SiNx interlayer is introduced between the GaN layer and the silicon substrate to act as a stress buffer. This intermediary layer has mechanical and thermal properties that are intermediate between GaN and silicon, reducing the lattice mismatch and thermal expansion coefficient difference. The SiNx layer absorbs and distributes the stress, preventing crack formation while still allowing the GaN layer to grow thick enough to reduce threading dislocation density.
Solution Approach 2:
The patent changes the physical and chemical parameters of the interface between GaN and silicon substrate by introducing SiNx. This alters the thermal expansion coefficient matching and mechanical stress distribution. The SiNx layer has a thermal expansion coefficient that is closer to GaN than silicon, and its mechanical properties provide a transition zone that reduces the stress concentration at the interface, enabling thick GaN growth without wafer deformation or cracking.
2Reliability
If the GaN layer is made thicker to improve device quality, then internal quantum efficiency improves, but wafer bowing and cracking increase
Solution Approach 1:
The SiNx interlayer serves as a stress-compensating intermediary that enables the growth of thick GaN layers. By positioning this layer at the GaN-silicon interface, it provides continuous stress distribution throughout the thick GaN layer, preventing the accumulation of tensile stress that would otherwise cause wafer bowing and cracking. This allows the GaN layer to achieve the thickness required for high internal quantum efficiency while maintaining wafer flatness.
Solution Approach 2:
The SiNx layer is specifically chosen because its thermal expansion coefficient is intermediate between GaN and silicon. During the thermal processes of GaN growth and device operation, this thermal expansion matching reduces the differential thermal stress that causes wafer deformation. The SiNx layer expands and contracts at a rate that is compatible with both GaN and silicon, preventing the development of large thermal stresses that would lead to bowing and cracking in thick wafers.
3Adaptability or versatility
If n-type doping is added to GaN layers to improve electrical performance, then device functionality improves, but tensile stress and crack formation increase
Solution Approach 1:
The SiNx interlayer acts as a stress buffer that compensates for the additional tensile stress introduced by n-type doping. The doping process creates more carriers and improves electrical performance, but also increases the tensile stress in the GaN layer. The SiNx layer, with its different mechanical properties, absorbs and distributes this additional stress, preventing the initiation and propagation of cracks that would otherwise occur in doped GaN layers on silicon substrates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in GaN layers with significantly reduced threading dislocations, enabling the growth of high-quality, crack-free layers on silicon substrates, improving the internal quantum efficiency of LEDs and allowing for larger, more cost-effective wafer production.
Implementation Method 1
A consequence of the mismatched lattice parameters and thermal expansion coefficients, particularly where the difference lies between the substrate and the overlying layers, is a high degree of curvature that is introduced into the wafer by the mismatch
Implementation Method 2
One way to reduce the dislocation density is to rely on the growth of interlayers, as described in US2002/0069817
Data Source
Figure 1
Figure 2~3
AI summary
The present invention provides a semiconductor wafer comprising: a substrate layer; and a first GaN layer having one or more SiNx interlayers therein; and wherein in the first GaN layer at least one SiNx interlayer has GaN penetrated through one or more portions of said SiNx interlayer and preferably has a thickness of from 0.5 to 10nm.