Selective Diffusion Barrier Removal for GaN Source/Drain Contacts

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Metallic diffusion barriers in III-Nitride transistors, such as titanium nitride, increase resistance between source/drain contacts and underlying regions, diminishing the performance of transistors like III-Nitride HEMTs by reducing current carrying capability and speed.

Innovation Solution

A method for fabricating highly conductive source/drain contacts in III-Nitride transistors involves forming dielectric trenches, depositing a thin gate dielectric layer, applying a diffusion barrier material, and selectively removing it from source and drain regions while maintaining it over the gate area, followed by deposition of ohmic metal contacts, which results in reduced contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If metallic diffusion barriers (such as titanium nitride) are used in source/drain regions, then diffusion protection is provided, but resistance between source/drain contacts and underlying regions increases

Engineering Contradiction:
Improvediffusion protectionVSAvoidcontact resistance
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies different treatments to different regions: diffusion barrier material is selectively removed from source/drain contact regions while retained in gate regions. This local differentiation allows low resistance at contacts (by removing barrier) while maintaining diffusion protection at gates (by retaining barrier), thus resolving the contradiction between diffusion protection and low contact resistance.

Inventive Principle:
Principle #3Local quality

2Reliability

If metallic diffusion barriers are used throughout the transistor, then diffusion protection is maintained, but transistor speed and current carrying capability are reduced

Engineering Contradiction:
Improvediffusion protectionVSAvoidtransistor speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The invention selectively removes diffusion barrier material from source/drain contact regions while preserving it in gate regions. This local quality approach enables high-speed operation at contacts (by removing barrier) while maintaining reliable diffusion protection at gates, thus resolving the contradiction between diffusion protection and transistor speed.

Inventive Principle:
Principle #3Local quality

3Loss of energy

If diffusion barrier material is removed from source/drain regions, then contact resistance is reduced, but diffusion protection is compromised

Engineering Contradiction:
Improvecontact resistanceVSAvoiddiffusion protection
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent selectively removes diffusion barrier material only from source/drain contact regions where low resistance is critical, while deliberately retaining the barrier material in gate regions where diffusion protection is essential. This spatially differentiated approach resolves the contradiction by applying different material presence strategies to different functional regions.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The invention segments the transistor structure into distinct regions (source/drain contacts versus gate regions) and applies different material configurations to each segment. This segmentation allows optimized performance for each region's specific function, resolving the contradiction between low contact resistance and diffusion protection.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10074729B2Forming highly conductive source/drain contacts in III-Nitride transistors
Publication Date: 2018.09.11 INFINEON TECHNOLOGIES AMERICAS CORP
  • US10074729B2 patent drawing
  • US10074729B2 patent drawing
  • US10074729B2 patent drawing

AI summary

In one embodiment, a method for fabricating a III-Nitride transistor on a III-Nitride semiconductor body is disclosed. The method comprises etching dielectric trenches in a field dielectric overlying gate, source, and drain regions of the III-Nitride semiconductor body, and thereafter forming a gate dielectric over the gate, source and drain regions. The method further comprises forming a blanket diffusion barrier over the gate dielectric layer, and then removing respective portions of the blanket diffusion barrier from the source and drain regions. Thereafter, gate dielectric is removed from the source and drain regions to substantially expose the source and drain regions. Then, ohmic contacts are formed by depositing contact metal in the source and drain regions. The method results in highly conductive source/drain contacts that are particularly suitable for power transistors, for example, III-Nitride transistors, such as GaN transistors. In another embodiment, a structure for highly conductive source/drain contacts is disclosed.