Stepped GaN Gate and Field Plate Layout for Lower Capacitance
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Solution Overview
Problem
Conventional methods for reducing gate resistance in GaN transistors often result in increased gate-drain capacitance and gate-source capacitance, leading to reduced gain and cut-off frequency, which complicates meeting device performance requirements for RF and power applications.
Innovation Solution
The implementation of a GaN heterojunction field effect transistor (HFET) with a stepped configuration for both the gate electrode and the field plate structure, featuring at least one gate field plate (GFP) and multiple source-connected field plates (SFPs), which are fully self-aligned with the gate channel to minimize device-to-device performance variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If accurate alignment of gate channel and field plate is achieved, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The gate electrode and field plate structure are formed simultaneously using a common etch process with the channel. This preliminary alignment action ensures that the gate and field plate are automatically positioned relative to the channel before subsequent processing steps, eliminating the need for separate alignment operations and reducing manufacturing complexity.
Solution Approach 2:
The stepped configuration of the gate electrode and field plate structure creates self-alignment features where the horizontal extents of different gate levels and the field plate are inherently positioned relative to each other through the etch selectivity and layer thickness control, reducing the need for external alignment interventions.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, surface passivation over the semiconductor substrate, and a first interlayer dielectric over the surface passivation. A gate electrode includes a gate channel portion that extends through the surface passivation to contact the upper surface of the semiconductor substrate, a first gate field plate with a first horizontal bottom extent that overlies the upper surface of the surface passivation, and a second gate field plate with a second horizontal bottom extent that is higher than the first horizontal bottom extent. A conductive field plate includes a first field plate with a third horizontal bottom extent that overlies and contacts the upper surface of the surface passivation, and a second field plate with a fourth horizontal bottom extent that is at least as high as the first horizontal bottom extent of the first gate field plate.