GaN Semiconductor Substrate Trench Segmentation for Crack Mitigation
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Solution Overview
Problem
GaN-type semiconductor substrates face reliability issues due to thermal expansion mismatch between silicon and gallium nitride, leading to cracks and high defect densities, which are insufficient for high-power applications like power converters requiring high breakdown voltages.
Innovation Solution
The introduction of trenches in the semiconductor substrate to increase the length of parasitic conductive paths, combined with a Ga-rich second sublayer and a buried insulating layer, allows for regular monocrystalline growth of GaN-type layers, enhancing breakdown voltage and reducing defect density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a silicon substrate is used as a carrier for GaN layers, then the manufacturing process is simplified and cost is reduced, but thermal expansion mismatch causes cracks and high defect densities reducing reliability
Solution Approach 1:
The patent introduces trenches that segment the silicon substrate into isolated regions, preventing crack propagation across the entire substrate. The trenches divide the continuous substrate into separate segments, allowing the GaN layer stack to be isolated in regions free from substrate-induced defects while maintaining the advantage of using silicon as the base substrate.
Solution Approach 2:
The patent extracts or removes the problematic continuous substrate structure by introducing trenches that eliminate the harmful thermal expansion mismatch effect. By removing the continuous substrate connection and replacing it with trench structures filled with dielectric material, the patent eliminates the source of cracks and defects while retaining silicon substrate benefits.
2Reliability
If the top layer of substrate or buffer layer is patterned to reduce mismatch, then crack formation is reduced, but manufacturing complexity increases due to additional processing steps
Solution Approach 1:
Instead of patterning the top layer or buffer layer as in prior art, the patent segments the substrate itself by introducing trenches. This approach achieves crack-free growth by isolating the GaN layer stack in trench-defined regions, while the segmentation is achieved at the substrate level rather than requiring complex top-layer patterning processes.
Solution Approach 2:
The patent moves the mismatch mitigation strategy from the lateral dimension (patterning top layers) to the vertical dimension by introducing trenches that extend through the substrate. This dimensional change allows crack prevention through vertical isolation rather than lateral patterning, simplifying the overall manufacturing process.
3Reliability
If localized growth on islands is used to reduce defect density, then defect density decreases, but growth time increases substantially
Solution Approach 1:
The patent performs preliminary action by pre-forming trenches in the substrate before growing the GaN layer stack. This preliminary structuring creates predefined growth regions that guide subsequent epitaxial growth, allowing defects to be confined to trench regions while maintaining efficient growth in the active device regions. The preliminary trench formation eliminates the need for extended growth times associated with lateral coalescence methods.
Solution Approach 2:
The patent applies local quality by creating distinct regions with different functions: trench regions for defect confinement and isolated substrate regions for high-quality GaN growth. This local differentiation allows the system to tolerate defects in specific areas while maintaining high reliability in the active device regions, achieving defect reduction without sacrificing growth efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases the breakdown voltage of GaN-type semiconductor devices, making them suitable for high-power applications by reducing parasitic conductive paths and improving crystal growth, thus addressing the limitations of existing substrate structures.
Implementation Method 1
A GaN-type layer stack comprising a buffer layer, a first and a second active layer is grown thereon
Implementation Method 2
Particularly due to the difference in thermal expansion between f.i. silicon and gallium nitride, formation of cracks as well as relatively high defect densities have been found
Data Source
Figure 1(a)~1(c)
Figure 2
Figure 3a~3d
AI summary
The semiconductor substrate structure (100) a semiconductor substrate (1) and a GaN-type layer stack (20) on top of the semiconductor substrate (1). The GaN-type layer stack (20) comprises at least one buffer layer (21,22), a first active layer (2) and a second active layer (23), at an interface of which first and second active layer (2,3) active device regions are definable. The semiconductor substrate (1) is present on an insulating layer (12) and is patterned to define trenches (14) according to a predefined pattern, which pattern comprises at least one trench (14) underlying such active device region, said trenches (14) extending from the insulating layer (12) into at least one buffer layer (21,22) of the GaN-type layer stack (20) and being overgrown within said at least one buffer layer (22), so as to obtain that the first and the second active layer (2,3) are continuous at least within the active device regions.