GaN Substrate Via Contact Layout for Higher Current Density
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Solution Overview
Problem
Integrating suitable substrate contacts between GaN devices and silicon substrates to maintain constant bias and handle higher currents has been challenging, particularly in achieving desired circuit density.
Innovation Solution
A microelectronic device with a substrate via opening extending through the III-N semiconductor layer to the semiconductor substrate, featuring a substrate contact pad and an inter-level dielectric layer with a planar surface, facilitating electrical connections and reducing device area through precise photolithography processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If substrate contacts are integrated into silicon substrates to maintain constant bias and enable higher current handling, then electrical functionality is improved, but device area increases
Solution Approach 1:
The patent transitions from planar substrate contacts to vertical through-silicon vias (TSVs) that extend through the entire thickness of the silicon substrate. This dimensional change from 2D to 3D allows electrical connections to be made through the substrate volume rather than requiring large surface area contacts, thereby improving current handling capability while minimizing device footprint.
Solution Approach 2:
The substrate contacts are nested within the III-N semiconductor layer structure. The through-silicon vias are formed by etching through the silicon substrate and then filling with conductive material that is subsequently integrated with the III-N layer, creating a nested configuration where the contact structure is embedded within the semiconductor device architecture rather than occupying separate device area.
2Productivity
If narrower interconnect lines and spaces are used to reduce device area, then circuit density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary planarization of the silicon substrate surface before forming the III-N semiconductor layer and subsequent interconnect structures. This preliminary action creates a flat baseline surface that facilitates the formation of narrower interconnect lines and spaces with better dimensional control, reducing the manufacturing precision challenges that would otherwise arise from substrate roughness or warpage.
Solution Approach 2:
By moving substrate contacts to the vertical dimension through TSV formation, the patent frees up lateral space that can then be utilized for narrower interconnect lines and higher circuit density. The vertical routing of contacts through the substrate thickness allows lateral interconnect dimensions to be reduced without compromising electrical functionality.
Data Source
AI summary
A microelectronic device includes a semiconductor substrate with a III-N semiconductor layer over the semiconductor substrate. A substrate via opening extending through the III-N semiconductor layer and a substrate contact pad in the substrate via opening, contacting the semiconductor substrate provide a substrate contact. The microelectronic device also includes an inter-level dielectric layer with a planar surface over the substrate contact. The microelectronic device further includes an interconnect metal level over the inter-level dielectric layer. The substrate via opening is formed through the III-N semiconductor layer to expose the semiconductor substrate. The substrate contact pad is formed over the III-N semiconductor layer, extending into the substrate via opening and making contact with the semiconductor substrate, to form the substrate contact. The ILD layer is formed over the III-N semiconductor layer and the substrate contact pad, so that the ILD layer has a planar surface over the substrate via opening.