GaN Superjunction Transistor With Back-Side Field Management
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Solution Overview
Problem
Gallium nitride (GaN) transistors face challenges in managing high electric fields and have high on-resistance due to the lack of effective back-side field management, limiting their performance in high-frequency and high-power applications.
Innovation Solution
The technique involves increasing the number of current paths (channels) in GaN transistors without increasing device area by using p-type implantation into the substrate, forming a superjunction device, and implementing back-side field management to reduce on-resistance and improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of current paths (channels) in GaN transistor is increased, then the current capacity is improved, but the device area increases
Solution Approach 1:
The patent transitions from a single-plane current path architecture to a three-dimensional stacked heterostructure with multiple 2DEG channels at different vertical levels. By forming first and second compound semiconductor heterostructures with respective 2DEG channels at different heights, the device achieves multiple current paths without increasing the planar footprint, effectively utilizing the vertical dimension to increase current capacity.
2Device complexity
If conventional GaN heterostructure is used, then the device structure is simple, but the on-resistance is high
Solution Approach 1:
The patent divides the current conduction path into multiple parallel segments by creating separate first and second 2DEG channels within stacked heterostructures. Each heterostructure layer pair forms an independent conductive channel, segmenting the total current flow into multiple paths that operate in parallel, thereby reducing the overall on-resistance while maintaining structural organization.
3Ease of manufacture
If back-side field management is not implemented, then the device fabrication is simpler, but the electric field distribution is non-uniform
Solution Approach 1:
The patent incorporates p-type semiconductor material layers during the initial fabrication process, forming them as integral parts of the stacked heterostructure before device operation. This preliminary incorporation of field management elements ensures uniform electric field distribution is built into the device architecture from the start, avoiding the need for separate post-fabrication field management steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach doubles the current capacity and halves the on-resistance of GaN transistors, enhancing their performance and efficiency in high-power applications by creating a more uniform electric field profile.
Implementation Method 1
utilize back-side field management to improve the device's performance. For example, the techniques can include using p-type implantation into the substrate, e.g., silicon carbide (SiC), as a field management tool to form a superjunction device, thereby increasing the effective field and reducing the on-resistance multiplied by the output charge (Qoss)
Implementation Method 2
The two-dimensional electron gas (2DEG) channels formed by GaN based heterostructures generally have high electron mobility, making devices fabricated using these structures useful in power-switching and amplification systems
Implementation Method 3
a conductive material extending vertically between and electrically coupling the buried first 2DEG channel and the topside second 2DEG channel
Data Source
AI summary
Techniques to increase the number of current paths (or “channels”) in a GaN transistor, without increasing the device area, thereby decreasing the on-resistance. In addition, this disclosure describes techniques to utilize back-side field management to improve the device's performance. For example, the techniques can include using p-type implantation into the substrate, e.g., silicon carbide (SiC), as a field management tool to form a superjunction device, thereby increasing the effective field and reducing the on-resistance multiplied by the output charge (Qoss).


