GaN Superjunction Vertical JFET Structure for Low On-Resistance
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Solution Overview
Problem
Conventional power electronic devices face challenges in achieving low specific on-resistance while maintaining high breakdown voltages, leading to increased die size and power loss.
Innovation Solution
The use of a super junction structure in vertical JFET and MOSFET devices, specifically employing III-nitride materials and epitaxial regrowth techniques, reduces specific on-resistance up to 10-100 times without compromising breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional power electronic devices are used, then breakdown voltage can be maintained, but specific on-resistance increases and die size increases
Solution Approach 1:
The drift region is segmented into multiple alternating n-type and p-type columns forming a superjunction structure. This segmentation allows the device to achieve low on-resistance through optimized charge compensation while maintaining high breakdown voltage, thereby reducing the required die size for a given power handling capability
Solution Approach 2:
Different regions of the device are assigned different doping types and concentrations - n-type columns for charge storage, p-type columns for field termination. This local differentiation enables simultaneous optimization of on-resistance in the channel region and breakdown voltage at the device periphery, reducing overall die size requirements
2Reliability
If higher breakdown voltage is achieved, then power handling increases, but specific on-resistance increases
Solution Approach 1:
The superjunction structure enables independent optimization of doping parameters - the n-type columns are heavily doped to provide charge storage for low on-resistance, while the p-type columns are lightly doped to extend depletion region and increase breakdown voltage. This parameter differentiation resolves the traditional trade-off between these two critical parameters
Solution Approach 2:
The device employs a composite structure combining n-type and p-type semiconductor columns in a periodic array. This composite architecture leverages the complementary properties of opposite polarity doped regions to simultaneously achieve low specific on-resistance through charge compensation and high breakdown voltage through extended depletion regions
3Ease of manufacture
If conventional structures are used, then manufacturing is simpler, but reverse recovery time increases
Solution Approach 1:
The p-type columns are formed in advance during the epitaxial growth process before device operation, pre-positioning the charge compensation regions. This preliminary structuring enables faster reverse recovery by having the charge compensation mechanism already in place, eliminating the need for slower conventional charge removal processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in devices with lower specific on-resistance and faster reverse recovery times, enabling smaller die sizes and improved switching characteristics.
Implementation Method 1
epitaxially regrowing a second III-nitride structure in the trenches, wherein the second III-nitride structure is characterized by a second conductivity type opposite to the first conductivity type
Data Source
AI summary
A method for manufacturing a vertical JFET includes providing a III-nitride substrate having a first conductivity type and forming a first III-nitride layer coupled to the III-nitride substrate. The first III-nitride layer is characterized by a first dopant concentration and the first conductivity type. The method also includes forming a plurality of trenches within the first III-nitride layer and epitaxially regrowing a second III-nitride structure in the trenches. The second III-nitride structure is characterized by a second conductivity type. The method further includes forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions, and epitaxially regrowing a III-nitride gate layer in the recess regions. The III-nitride gate layer is coupled to the second III-nitride structure and the III-nitride gate layer is characterized by the second conductivity type.