GaN Surge Protection Element with Integrated Avalanche Resistance
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Solution Overview
Problem
GaN-based transistors have low avalanche resistance, making them prone to breakdown when subjected to surge voltages exceeding their rated breakdown voltage, and existing solutions require complex and costly processes to enhance this resistance.
Innovation Solution
A surge protection element is designed with a substrate, semiconductor multi-layer, p-type semiconductor layers, and electrodes to absorb excess voltage, including diodes and resistances that allow for reliable current conduction and voltage absorption without the need for additional manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a diode including Si having a high avalanche resistance is integrated on a substrate of the GaN-based transistor, then the avalanche resistance is improved, but the device complexity and manufacturing cost increase due to requiring an extra process for forming the diode in a Si substrate
Solution Approach 1:
The patent merges the surge protection function into the GaN-based transistor structure itself by forming a pn junction between the p-type semiconductor layer and the n-type semiconductor layer within the same device structure. This eliminates the need for separate external diodes or additional substrate integration processes, thereby improving avalanche resistance without increasing manufacturing complexity
Solution Approach 2:
The GaN-based transistor structure is designed to serve dual functions: normal transistor operation and surge protection through avalanche breakdown. The pn junction formed within the transistor structure provides both the rectification function and the avalanche protection function, making the device multi-functional and eliminating the need for separate protection components
2Reliability
If a diode including Si having a high avalanche resistance is integrated on a substrate of the GaN-based transistor, then the avalanche resistance is improved, but the manufacturing cost increases due to requiring an extra process for forming the diode in a Si substrate
Solution Approach 1:
The surge protection function is merged into the transistor fabrication process itself. The p-type and n-type semiconductor layers are formed using the same epitaxial growth or implantation processes already required for transistor manufacturing, eliminating the need for separate diode formation processes and reducing overall manufacturing cost
Solution Approach 2:
The transistor structure itself provides the avalanche protection function through its internal pn junction. The device serves its own protection needs without requiring external protection components or additional processing steps, making the manufacturing process more cost-effective
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly increases the avalanche resistance of power devices, allowing them to withstand surge voltages without breaking down, while simplifying the manufacturing process and reducing costs by integrating the surge protection element with the transistor on a single chip.
Implementation Method 1
the surge protection element according to one embodiment of the present disclosure includes: a substrate; a semiconductor multi-layer disposed above the substrate and including a channel and comprising a nitride semiconductor; a first p-type semiconductor layer and a second p-type semiconductor layer which are disposed above the semiconductor multi-layer; a first electrode disposed above the first p-type semiconductor layer; and a second electrode disposed above the second p-type semiconductor layer
Data Source
AI summary
A semiconductor element is provided which does not break down by avalanche current. A surge protection element includes: a semiconductor multi-layer comprising a nitride semiconductor; a first p-type semiconductor and a second p-type semiconductor which are disposed above the semiconductor multi-layer; a first electrode disposed above the first p-type semiconductor; and a second electrode disposed above the second p-type semiconductor.