Three-Terminal Bidirectional GaN Switch With Low Leakage and Resistance

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Solution Overview

Problem

Existing bidirectional GaN FET switches with dual gates have high channel resistance due to current flowing under two gates, and those with a single gate often have increased gate leakage current when reduced to three terminals.

Innovation Solution

A three-terminal bidirectional GaN FET switch is formed by integrating a single-gate GaN FET in parallel with back-to-back GaN FETs, where the source terminal of the back-to-back FETs is omitted and the field plate is connected to the source, reducing gate leakage current and channel resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If back-to-back GaN FETs with dual gates are used to achieve bidirectional high voltage blocking capability, then voltage blocking capability is improved, but channel resistance increases due to current flowing under two gates

Engineering Contradiction:
Improvevoltage blocking capabilityVSAvoidchannel resistance
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The device is segmented into two functional parts: a single-gate bidirectional GaN FET that handles high current with low resistance, and a back-to-back GaN FET structure that provides voltage blocking capability. Each segment performs its specialized function, resolving the contradiction between low channel resistance and high voltage blocking capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent merges two different GaN FET configurations (single-gate bidirectional FET and back-to-back FETs) into a single integrated device. The single-gate FET provides low-resistance current path while the back-to-back FETs provide symmetric voltage blocking, achieving both low channel resistance and high voltage blocking capability simultaneously.

Inventive Principle:
Principle #5Merging (Combining)

2Device complexity

If a single-gate bidirectional GaN FET is used to reduce device complexity, then device complexity is reduced, but gate leakage current increases when reduced to three terminals

Engineering Contradiction:
Improvedevice complexityVSAvoidgate leakage current
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The back-to-back GaN FET structure acts as an intermediary element that addresses the gate leakage issue. By incorporating this structure with a common source terminal, the device achieves three-terminal configuration while the back-to-back FETs help control and reduce gate leakage current through their symmetric structure and voltage blocking capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Strength

If back-to-back GaN FETs with common source are integrated in parallel with single-gate bidirectional GaN FET, then bidirectional voltage blocking capability is improved, but device complexity increases

Engineering Contradiction:
Improvebidirectional voltage blocking capabilityVSAvoiddevice complexity
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The integrated device achieves multi-functionality by combining two GaN FET structures that share common terminals. The single-gate bidirectional FET and back-to-back FETs share source/drain terminals and gate control, allowing the device to perform both low-resistance switching and symmetric voltage blocking functions simultaneously, reducing overall device complexity despite the sophisticated internal structure.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240234513A9THREE-TERMINAL BIDIRECTIONAL ENHANCEMENT MODE GaN SWITCH
Publication Date: 2024.07.11 EFFICIENT POWER CONVERSION CORP
  • US20240234513A9 patent drawing
  • US20240234513A9 patent drawing
  • US20240234513A9 patent drawing

AI summary

A three-terminal bidirectional GaN FET with a single gate. The device is formed by integrating a single-gate bidirectional GaN FET in parallel with a bidirectional device formed of two back-to-back GaN FETs with a source that is connected to the field plate of the device and does not have a pin-out. Diodes or gate-shorted-to-source FETs are connected between the source without pin-out and the D/S and S/D power terminals of the device. In another embodiment, a single-gate bidirectional GaN FET is provided with diodes or gate-shorted-to-source FETs connected between the substrate and the power terminals of the device.