GaN Switching Device Reducing Parasitic Capacitance
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Solution Overview
Problem
The existing semiconductor devices with a 4-terminal structure suffer from high parasitic capacitance and impedance due to the proximity of the JG electrode and drain electrode, leading to slow switching speeds and interference with high-speed switching operations.
Innovation Solution
A semiconductor device with a heterojunction structure featuring a recessed gate insulating film and a MOS gate electrode, where the JG electrode is directly coupled to the source electrode through an electrode layer, reducing parasitic resistance and capacitance by minimizing the overlap area with the drain electrode, and optimizing the distance between the p-GaN and u-GaN layers to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the JG electrode and drain electrode are disposed close to each other to reduce device area, then the device area is reduced, but the parasitic capacitance between the JG electrode and drain electrode increases, causing slow switching speed
Solution Approach 1:
The patent introduces a vertical dimension by forming a recess portion in the second semiconductor layer beneath the gate structure portion. The end of the third semiconductor layer protrudes toward the drain electrode in the horizontal direction, while the recess portion extends in the vertical direction. This multi-dimensional arrangement allows the JG electrode to be coupled to the source electrode through the electrode layer while minimizing the overlap area with the drain electrode, thereby reducing parasitic capacitance without significantly increasing device area.
2Reliability
If the JG electrode and source electrode are connected through a bonding wire to achieve electrical connection, then the electrodes are electrically connected, but the impedance between the JG electrode and source electrode becomes large, interfering with high-speed switching
Solution Approach 1:
The patent merges the JG electrode and source electrode into a single integrated structure by coupling them through an electrode layer formed on the interlayer insulating film. This direct coupling eliminates the need for separate bonding wire connections, significantly reducing the impedance between the JG electrode and source electrode, and enabling high-speed switching operations.
3Object-affected harmful factors
If the overlap area between the third semiconductor layer and drain electrode is reduced to minimize parasitic capacitance, then the parasitic capacitance is reduced, but the device area increases
Solution Approach 1:
The patent utilizes vertical spacing by forming a recess portion in the second semiconductor layer. The end of the third semiconductor layer protrudes toward the drain electrode in the horizontal direction by a controlled distance (0 μm to 5 μm), while the recess portion provides vertical separation. This multi-dimensional approach minimizes the overlap area between the third semiconductor layer and drain electrode, reducing parasitic capacitance without significantly increasing the horizontal device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables faster charging of parasitic capacitance and reduces impedance, allowing for high-speed switching by minimizing the parasitic capacitance and resistance, thereby accelerating the turn-off process of the switching device.
Implementation Method 1
a parasitic capacitance formed between the JG electrode and the drain electrode, to be more specific, a parasitic capacitance formed by a polarization junction is large
Data Source
AI summary
A semiconductor device has a lateral switching device that includes a channel forming layer, a gate structure portion, a source electrode, a drain electrode, a third semiconductor layer, a fourth semiconductor layer, and a junction gate electrode. The gate structure portion has a gate insulating film provided in a recess portion of the channel forming layer and a MOS gate electrode functioning as a gate electrode of a MOS structure provided on the gate insulating film. The source electrode and the junction gate electrode are coupled through an electrode layer provided on an interlayer insulating film covering the MOS gate electrode. An end of the third semiconductor layer facing the drain electrode protrudes toward the drain electrode from an end of the fourth semiconductor layer facing the drain electrode by a distance in a range of 1 μm to 5 μm both inclusive.