GaN ELO Template Separation for Low-Defect Through-Hole Formation

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Solution Overview

Problem

Current methods for manufacturing semiconductor devices using sapphire substrates with GaN buffer layers face challenges in efficiently forming through-holes and separating the semiconductor parts from the template substrate, leading to defects and reduced light emission efficiency.

Innovation Solution

The method involves preparing a template substrate with a mask pattern and opening portions, forming semiconductor parts using the ELO method, and selectively etching the main substrate and semiconductor parts to facilitate separation, while optimizing the etching process to reduce defects and enhance light emission efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If through-holes are formed in sapphire substrate and GaN buffer layer to take out electrodes, then electrode contact is achieved, but manufacturing complexity and defect risk increase

Engineering Contradiction:
Improveelectrode contact reliabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the template substrate removal process into two distinct stages: first removing the sapphire substrate in regions corresponding to opening portions, then removing the GaN buffer layer in the same regions. This segmentation allows each removal step to be optimized independently, reducing overall manufacturing complexity while maintaining electrode contact reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by forming a mask pattern on the template substrate before removing the sapphire substrate. This mask pattern pre-defines the regions where through-holes will be formed, guiding the subsequent substrate removal process and ensuring accurate electrode positioning, thereby reducing manufacturing complexity and defect risk.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If conventional etching methods are used to separate semiconductor parts from template substrate, then separation is achieved, but light emission efficiency decreases due to defects

Engineering Contradiction:
Improveseparation efficiencyVSAvoidlight emission efficiency
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by using selective etching methods that target specific crystal orientations of the GaN buffer layer. Different etching conditions are applied to different regions based on their crystal orientation, allowing clean separation in some areas while preserving light emission quality in others, thus maintaining high light emission efficiency during separation.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes etching parameters (such as etchant composition, temperature, and processing time) to optimize the separation process. By adjusting these parameters, the etching rate and selectivity are controlled to achieve clean separation of semiconductor parts from the template substrate without creating defects that would reduce light emission efficiency.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If mask pattern with opening portions is used for selective growth, then manufacturing precision improves, but process steps increase

Engineering Contradiction:
Improvesemiconductor part positioning precisionVSAvoidnumber of process steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The mask pattern serves multiple functions: it defines the opening portions for selective epitaxial growth, guides the subsequent sapphire substrate removal, and determines the final positioning of semiconductor parts. This multi-functionality reduces the need for additional alignment and positioning steps, thereby maintaining manufacturing precision without proportionally increasing process complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The mask pattern is formed in advance on the template substrate before the epitaxial growth process. This preliminary action pre-establishes the geometric constraints and positioning references needed for precise semiconductor part formation, eliminating the need for subsequent realignment operations and reducing overall process complexity.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the efficient separation of semiconductor devices from the template substrate, reducing defects and improving light emission efficiency by controlling the etching process and using specific etching rates for polar and semipolar planes.

Implementation Method 1

forming a first semiconductor part on the mask pattern by using an ELO method

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 2

a step of removing a portion of the main substrate overlapping the opening portion in plan view and a step of removing a portion of the first semiconductor part overlapping the opening portion in plan view

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS20240313151A1Semiconductor device manufacturing method and manufacturing apparatus, semiconductor device and electronic device
Publication Date: 2024.09.19 KYOCERA CORP
  • US20240313151A1 patent drawing
  • US20240313151A1 patent drawing
  • US20240313151A1 patent drawing

AI summary

A manufacturing method of a semiconductor device includes a step of preparing a template substrate including a main substrate and a mask pattern located above the main substrate and including a mask portion and an opening portion, a step of forming a first semiconductor part on the mask pattern by using an ELO method, a step of removing a portion of the main substrate overlapping the opening portion in plan view; and, a step of removing a portion of the first semiconductor part overlapping the opening portion in plan view.