GaN Transistor T-Gate Sidewall Extensions for Leakage Reduction
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Solution Overview
Problem
High-speed gallium nitride transistor devices face challenges with increased gate and drain leakage currents and reduced breakdown voltage due to shrinking gate lengths and higher electron concentration, which also degrade the unity current gain cutoff frequency (fT) and maximum frequency of oscillation (fmax) when attempting to reduce leakage currents.
Innovation Solution
A high-frequency, high-voltage gallium nitride field effect transistor device is developed with a thin dielectric passivation layer and gate electrode sidewall extensions spaced apart from the passivation layer, coated with conformal dielectric layers to form a vertical metal-insulator-semiconductor (MIS) sandwich, reducing leakage currents and maintaining high-voltage operation while minimizing capacitance increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate length is shrunk and electron concentration is increased to improve device speed, then device speed and power handling capability are improved, but gate and drain leakage currents increase and breakdown voltage is reduced
Solution Approach 1:
The patent introduces a vertical gap dimension between the gate electrode and passivation layer, transforming a two-dimensional planar structure into a three-dimensional structure with controlled spacing. This vertical separation reduces leakage current paths while maintaining the high-speed performance achieved through shrunk gate length and high electron concentration.
Solution Approach 2:
The patent introduces a dielectric layer as an intermediary between the gate electrode and the passivation layer. This intermediate dielectric material acts as a barrier that reduces leakage current while allowing the gate electrode to maintain its high-speed switching function through optimized gate length and electron concentration.
2Object-generated harmful factors
If device features and processing steps are added to reduce leakage current, then gate and drain leakage currents are reduced, but unity gate current cutoff frequency (fT) is degraded due to added gate capacitance
Solution Approach 1:
The patent applies local quality by introducing the dielectric layer and vertical gap only in specific regions where leakage current occurs, rather than uniformly across the entire device. This localized modification reduces leakage current while minimizing the added gate capacitance that would degrade fT, as the dielectric is positioned specifically at the gate-passivation interface where it is most effective.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves low off-state gate and drain leakage currents with high unity current gain cutoff frequency (fT) and maximum frequency of oscillation (fmax), ensuring reliable high-voltage operation and frequency performance.
Implementation Method 1
coated with conformal dielectric layers to form a vertical metal-insulator-semiconductor (MIS) sandwich, reducing leakage currents
Data Source
AI summary
A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11-43) covered by a passivation surface layer (43) in which a T-gate electrode with sidewall extensions (48) is formed and coated with a conformal passivation layer (49) so that the T-gate electrode sidewall extensions are spaced apart from the underlying passivation surface layer (43) by the conformal passivation layer (49).