T-Shaped GaN Gate Structure for Sub-0.1 µm Lithography
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Solution Overview
Problem
Current semiconductor manufacturing techniques, particularly for GaN-based high electron mobility transistors (HEMTs), face challenges in reducing the gate length of T-shaped gates due to equipment limitations, leading to low processing efficiency and difficulty in achieving smaller gate lengths.
Innovation Solution
The semiconductor device and method involve forming an epitaxial structure with a first passivation layer having a through hole and a recess, and a second passivation layer disposed in the recess. The gate structure passes through the through hole and is connected to the epitaxial structure, with curved side surfaces on the passivation layers to facilitate smaller gate lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If electron-beam lithography is used to fabricate gate electrodes with gate length smaller than 0.1 micrometers, then manufacturing precision is improved, but processing efficiency deteriorates due to point-by-point scanning
Solution Approach 1:
The gate structure is divided into two distinct parts: a narrow bottom surface (gate region) and a wide top portion (contact region). This segmentation allows each part to serve its specific function - the narrow bottom improves cutoff frequency while the wide top reduces resistance, avoiding the need for point-by-point scanning of a uniformly small gate structure
Solution Approach 2:
The invention transitions from a conventional planar gate to a three-dimensional T-shaped gate structure by adding vertical depth and creating overlapping layers. The gate electrode extends through a dielectric layer, creating a T-shaped cross-section that achieves small effective gate length at the semiconductor interface while maintaining large top surface area for electrical contact
2Productivity
If steppers are used for lithography with i-line ultraviolet light exposure, then processing efficiency is maintained, but manufacturing precision deteriorates as gate length cannot be reduced below 0.35 micrometers
Solution Approach 1:
The side surfaces of the passivation layers are designed as curved surfaces rather than flat surfaces. This curvature enables the formation of the T-shaped gate profile using conventional lithography, as the curved sides facilitate the etching process and allow the gate to achieve its characteristic shape with larger minimum features
Solution Approach 2:
The gate structure is nested within the passivation layers, with the gate electrode positioned inside the through-hole formed in the first passivation layer and the second passivation layer disposed within the through-hole. This nested configuration allows conventional lithography to define the outer boundaries while the nested structure achieves the required small effective gate dimensions
Data Source
AI summary
A semiconductor device including an epitaxial structure, a first passivation layer, a second passivation layer and a gate structure is prepared. The first passivation layer is disposed on the epitaxial structure and has a through hole and a recess that spatially communicates with the through hole. The through hole extends from a top surface of the first passivation layer to a bottom surface of the first passivation layer, and the recess is spaced apart from the epitaxial structure. The second passivation layer is disposed in the recess. The gate structure passes through the through hole and is connected to the epitaxial structure. The first passivation layer has a side surface that borders the recess and that is a curved surface.