GaN Transistor Contact Shape for Reduced Resistance
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Solution Overview
Problem
Gallium nitride (GaN) transistors face high contact resistance issues due to their large band-gap, which reduces their efficiency, especially in high-breakdown voltage applications required for 5G communication technologies.
Innovation Solution
The implementation of GaN transistors with non-planar source/drain (S/D) regions and roughened surfaces to increase the interface surface area, reducing contact resistance without expanding the footprint, achieved through epitaxial growth and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar contact surfaces are used in GaN transistors, then the device structure remains simple, but contact resistance is high which reduces efficiency
Solution Approach 1:
The patent transforms the conventional planar (2D) contact surface into a three-dimensional non-planar structure with multiple surfaces. By creating contact surfaces that extend in multiple dimensions rather than remaining flat, the total contact area is significantly increased, thereby reducing contact resistance without expanding the device footprint.
Solution Approach 2:
The patent introduces curved and non-planar contact surfaces instead of flat planes. The contact surfaces are formed with specific curvatures and angles (e.g., first contact surface at first angle, second contact surface at second angle) to maximize the interface area between the contact and the source/drain regions, thus reducing contact resistance.
2Reliability
If the contact footprint is increased to reduce contact resistance, then contact resistance decreases, but the device area increases
Solution Approach 1:
Instead of expanding the contact footprint in the planar direction, the patent utilizes the third dimension by creating non-planar contact surfaces that extend vertically and at angles. This allows the contact area to increase while maintaining the same planar footprint, thus reducing contact resistance without increasing device area.
Solution Approach 2:
The patent creates a nested contact structure where multiple contact surfaces are arranged within the same footprint boundary. The first and second contact surfaces are positioned at different angles and depths, effectively nesting multiple contact interfaces within the same planar area, thereby increasing total contact area without expanding the footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively decreases contact resistance, enhancing the efficiency of GaN transistors and supporting their use in high-breakdown voltage applications, particularly for 5G communication technologies.
Implementation Method 1
achieved through epitaxial growth and etching processes
Implementation Method 2
GaN transistors with non-planar source/drain (S/D) regions and roughened surfaces to increase the interface surface area
Data Source
Figure 1~2
Figure 3A~3C
Figure 4A~4B
AI summary
Embodiments described herein comprise a transistor device that comprises a GaN channel. In an embodiment, the transistor device further comprises a source region and a drain region. The source region may be separated from the drain region by the GaN channel. In an embodiment, the source region and the drain region comprise surfaces with a root mean squared (RMS) surface roughness greater than 3 nm. In an embodiment, the transistor device further comprises a gate electrode over the GaN channel, a source contact in contact with source region, and a drain contact in contact with the drain region.