Parallel GaN Transistor Layouts for Common Source Inductance Reduction
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Solution Overview
Problem
Gallium nitride (GaN) transistor devices experience undesirable effects from common source inductance and inter-device inductance, which can lead to unexpected gate turning on/off and potential overloading, especially in high-frequency and high-current applications.
Innovation Solution
The implementation of circuit layouts that spatially separate the gate and drain current loops, ensuring they remain perpendicular and decoupled, along with specific PCB layouts and electrical connections, to reduce the impact of common source inductance. This includes empirical formulas to optimize inductance and capacitance configurations, such as Equation 1 and Equation 2, which address the rate of change in current and voltage, and the strategic arrangement of gate and source inductances to minimize CSI effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple transistor devices are connected in parallel to increase current capability, then the power throughput and current handling capability are improved, but common source inductance and inter-device inductance cause unexpected gate turning on/off and potential overloading
Solution Approach 1:
The patent divides the gate control into separate independent paths for each transistor device in the parallel configuration. Each gate has its own dedicated gate driver and control signal routing, preventing the gate control of one device from being affected by transient currents in other devices. This segmentation eliminates the common source inductance coupling between parallel devices.
Solution Approach 2:
The patent extracts the gate control loops from the common source path by implementing separate gate driver circuits and independent control signal routing for each transistor. This removes the gate control function from the shared source inductance path, preventing transient currents from inducing unwanted gate voltages.
2Ease of manufacture
If conventional PCB layouts are used for parallel transistor devices, then ease of manufacture is improved, but common source inductance causes negative effects on switching performance
Solution Approach 1:
The patent applies different layout qualities to different regions of the PCB. The gate control traces are routed with minimal inductance and are physically separated from high-current drain and source paths. The gate driver circuits are positioned close to their respective transistor gates, while high-current paths are routed through low-inductance ground connections. This localized optimization of trace routing and component placement reduces common source inductance without significantly complicating the manufacturing process.
Data Source
AI summary
Parallel transistor circuits with reduced effects from common source induction. The parallel transistors include physical gate connections that are located electrically close to one another. The parallel circuits are arranged such that the voltage at the common gate connection resulting from transient currents across common source inductance is substantially balanced. The circuits include switching circuits, converters, and RF amplifiers.