GaN Transistor Punch-Through Reduction via Doping Segmentation

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Solution Overview

Problem

Gallium-nitride (GaN) power FETs with short channels experience punch-through limitations, restricting their maximum input voltage and preventing them from utilizing the full electrical strength of GaN, especially in integrated circuits where smaller transistors are preferred.

Innovation Solution

Incorporating an undoped GaN epitaxy layer above a doped epitaxy layer in GaN transistors, which can be discrete or have a graduated transition, to increase punch-through voltage without degrading mobility, allowing for enhanced control over depletion region size and increased doping in the doped layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the channel length is reduced to make smaller transistors for integrated circuits, then the transistor size is reduced and integration density is improved, but punch-through breakdown occurs at lower voltages limiting the maximum input voltage

Engineering Contradiction:
Improvetransistor sizeVSAvoidpunch-through breakdown voltage
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent applies local quality by creating a non-uniform doping profile within the drift region. Specifically, a first doping concentration is used in a first portion of the drift region closer to the depletion region, and a second, lower doping concentration is used in a second portion farther away. This localized variation in doping quality allows the structure to maintain low breakdown voltage in the heavily doped region while preserving high punch-through voltage in the lightly doped region, thus resolving the contradiction between small transistor size and high breakdown voltage reliability.

Inventive Principle:
Principle #3Local quality

2Reliability

If doping concentration is increased in the drift region to increase punch-through voltage, then punch-through breakdown is improved, but mobility of charge carriers is degraded

Engineering Contradiction:
Improvepunch-through voltageVSAvoidcharge carrier mobility
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent resolves this contradiction by applying local quality through spatially varying doping concentrations. The first portion of the drift region has higher doping concentration to provide adequate punch-through voltage, while the second portion has lower doping concentration to maintain high charge carrier mobility. This localized differentiation allows each region to optimize for its specific function without compromising the other.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The drift region is segmented into at least two distinct portions with different doping concentrations. The first portion (closer to the depletion region) has a first doping concentration optimized for breakdown characteristics, while the second portion (farther from the depletion region) has a second doping concentration optimized for carrier mobility. This segmentation allows independent optimization of conflicting properties in different spatial zones.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively limits punch-through effects, enabling GaN transistors to handle higher input voltages in the tens to hundreds of volts range while maintaining high mobility, thus optimizing their performance characteristics.

Implementation Method 1

a first epitaxy layer above the buffer layer, the first epitaxy layer having a first doping profile (for example, doped, or p-type doping); and a second epitaxy layer above the first epitaxy layer, the second epitaxy layer having a second doping profile (for example, undoped, or n-type doping)

Methodology Applied
Scientific EffectDoping: Dopants

Data Source

PatentUS10615280B2Reduced punchthrough breakdown in gallium-nitride transistors
Publication Date: 2020.04.07 INTEL CORP
  • US10615280B2 patent drawing
  • US10615280B2 patent drawing
  • US10615280B2 patent drawing

AI summary

There is disclosed in an example, a gallium nitride (GaN) field effect transistor (FET) having a gate, a drain, and a source, having: a doped GaN buffer layer; a first epitaxy layer above the buffer layer, the first epitaxy layer having a first doping profile (for example, doped, or p-type doping); and a second epitaxy layer above the first epitaxy layer, the second epitaxy layer having a second doping profile (for example, undoped, or n-type doping).