GaN Enhancement Mode Transistor Edge Termination Leakage

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Solution Overview

Problem

Existing Group III nitride-based transistor devices face challenges in improving edge termination structures to reduce gate/drain leakage and enhance performance, particularly for high-voltage applications.

Innovation Solution

The enhancement mode Group III nitride-based transistor device incorporates a p-doped Group III nitride runner and isolation ring with a recessed structure, which interrupts the two-dimensional carrier gas and heterojunction, and is laterally positioned between the isolation ring and the transistor cells to reduce gate/drain leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional edge termination structure is used in Group III nitride-based transistor devices, then the device can operate, but gate/drain leakage occurs and performance is limited

Engineering Contradiction:
Improvegate/drain leakage reductionVSAvoidedge termination structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The edge termination structure is segmented into multiple functional components: an isolation ring that locally interrupts the two-dimensional carrier gas, and a p-doped Group III nitride runner that provides additional electrical isolation. This segmentation allows each component to address specific aspects of leakage reduction, thereby improving reliability without creating an unmanageably complex structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The p-doped Group III nitride runner acts as an intermediary element positioned between the isolation ring and the transistor cells. It mediates the electrical isolation function by providing a controlled transition zone that prevents unwanted carrier gas formation while maintaining proper electrical connections, thus reducing gate/drain leakage effectively.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the p-doped Group III nitride runner is positioned closer to the transistor cells, then electrical isolation is improved, but unwanted carrier gas formation may occur

Engineering Contradiction:
Improveelectrical isolationVSAvoidunwanted carrier gas formation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The p-doped Group III nitride runner is selectively positioned at specific locations where electrical isolation is most critical, rather than uniformly across the entire device. This local application of doping creates zones of enhanced electrical isolation precisely where needed, preventing unwanted carrier gas formation without compromising overall device performance.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The doping concentration and spatial distribution of the p-doped Group III nitride runner are carefully controlled to optimize the balance between electrical isolation and carrier gas suppression. By adjusting these parameters, the structure achieves effective leakage reduction while preventing the formation of harmful carrier gas regions.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces gate/drain leakage and improves the performance of Group III nitride-based transistor devices, especially for high-voltage applications by maintaining electrical isolation and preventing unwanted carrier gas formation at the edge region.

Implementation Method 1

a Group III nitride barrier layer arranged on a Group III nitride channel layer, forming a heterojunction therebetween capable of supporting a two-dimensional carrier (charge) gas

Methodology Applied
Scientific EffectTwo-dimensional carrier gas formation at heterojunction: Hall Effect

Data Source

PatentUS11721754B2Enhancement mode transistor device
Publication Date: 2023.08.08 INFINEON TECH AUSTRIA AG
  • US11721754B2 patent drawing
  • US11721754B2 patent drawing
  • US11721754B2 patent drawing

AI summary

An enhancement mode Group III nitride-based transistor device includes a body having a first surface and a Group III nitride barrier layer arranged on a Group III nitride channel layer and forming a heterojunction therebetween. A first cell field includes transistor cells and an edge region. Each transistor cell includes source, gate and drain fingers extending substantially parallel to one another on the first surface in a longitudinal direction. The gate finger, arranged laterally between the source and drain fingers, includes a p-doped Group III nitride finger arranged between a metallic gate finger and the first surface. The edge region surrounds the transistor cells and includes an edge termination structure having an isolation ring and a p-doped Group III nitride runner. The isolation ring locally interrupts the heterojunction. The runner, extending transversely to the longitudinal direction, is located laterally between the isolation ring and an end of the drain finger.