GaN Power Transistor Embedded Packaging with Three-Level Interconnect
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Solution Overview
Problem
Conventional packaging solutions for lateral GaN power transistors face challenges such as high inductance, insufficient current handling, and thermal management issues, which limit the size and performance of these devices due to long wirebonds, mismatched thermal expansion coefficients, and increased package thickness.
Innovation Solution
A three-level interconnect structure with conductive layers and dielectric insulating layers is embedded within a package, featuring on-chip metallization, a copper redistribution layer, and a thick copper foil layer to provide low resistance and low inductance connections, along with a thermal pad for improved thermal management, allowing for larger current handling and reduced package profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wirebond packaging is used for large area lateral GaN power transistors, then device connectivity is achieved, but inductance increases and current handling capability deteriorates
Solution Approach 1:
The patent removes the wirebond interconnect layer entirely, extracting the harmful inductance source from the system. Instead of using wirebonds to connect the GaN die to the package, the invention directly bonds the die to a copper-clad substrate, eliminating the intermediate wirebond layer that causes high inductance and limiting current handling capability.
Solution Approach 2:
The patent transitions from a vertical wirebond connection approach to a planar direct-bond approach. By changing the interconnect geometry from three-dimensional wire loops to two-dimensional planar traces on the copper-clad substrate, the inductance is dramatically reduced while current handling capability is enhanced through broader contact areas.
2Reliability
If larger area contact pads are used to increase current handling, then current capability improves, but on-chip metallization resistance increases due to longer tracks
Solution Approach 1:
The patent segments the current path by distributing multiple contact pads across the GaN die surface rather than using a single large peripheral contact. This segmentation allows current to be collected from multiple distributed points, reducing the length and resistance of individual metallization tracks while maintaining high overall current handling capability.
Solution Approach 2:
The patent moves contact areas from the peripheral two-dimensional boundary to the three-dimensional active area of the device. By placing contact pads directly over the active region where current is generated, the metallization track length is minimized, reducing resistance while the vertical stacking of interconnect layers provides the necessary current handling capacity.
3Reliability
If conventional packaging structures are used, then device protection is achieved, but package thickness increases
Solution Approach 1:
The patent merges the package substrate and heat sink into a single integrated copper-clad substrate structure. The copper layer serves dual functions as both the electrical interconnect substrate and the thermal management heat sink, eliminating the need for separate thick package layers and reducing overall package thickness while maintaining device protection.
Solution Approach 2:
The copper-clad substrate performs multiple functions simultaneously: it provides mechanical support and protection for the GaN die, serves as the electrical interconnect layer for low-inductance connections, and acts as a heat sink for thermal management. This multi-functionality reduces the number of separate components needed, thereby reducing package thickness.
4Reliability
If copper interconnect layers are added to reduce inductance and increase current handling, then electrical performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent changes the electrical parameters of the interconnect by using thick copper layers with high conductivity instead of thin wirebonds. By altering the material parameters (copper vs. wirebond material) and geometric parameters (thick planar layers vs. thin wires), the inductance is reduced and current handling is improved while the manufacturing process remains relatively simple.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient current handling and thermal management, reducing energy loss and overheating, while maintaining a lower profile and cost-effectiveness compared to conventional wirebonded packages, thus enhancing the performance and practical size of GaN power transistors.
Implementation Method 1
first, second and third level interconnect comprising conductive interconnect layers
Implementation Method 2
intervening dielectric insulating layers
Implementation Method 3
a thermal pad for improved thermal management
Data Source
AI summary
Embedded packaging for devices and systems comprising lateral GaN power transistors is disclosed. The packaging assembly is suitable for large area, high power GaN transistors and comprises an assembly of a GaN power transistor and package components comprising a three level interconnect structure. In preferred embodiments, the three level interconnect structure comprises an on-chip metal layer, a copper redistribution layer and package metal layers, in which there is a graduated or tapered contact area sizing through the three levels for dividing/applying current on-chip and combining/collecting current off-chip, with distributed contacts over the active area of the GaN power device. This embedded packaging assembly provides a low inductance, low resistance interconnect structure suitable for devices and systems comprising large area, high power GaN transistors for high voltage/high current applications.