Multiple Field Plate GaN Transistor for High Breakdown Voltage
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Solution Overview
Problem
Existing power switching devices face limitations in achieving high breakdown voltages and low on resistances, particularly at high frequencies, due to electron trapping and electric field-related issues in GaN-based HEMTs.
Innovation Solution
The implementation of a multiple field plate transistor structure, which includes multiple insulating and conductive field plates electrically connected to the gate, reduces peak electric fields, enhances breakdown voltage, and minimizes trapping, thereby improving power performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single field plate structure is used in GaN HEMTs, then the device can achieve high electron mobility and good RF performance, but the breakdown voltage is limited and peak electric fields are high causing electron trapping
Solution Approach 1:
The single field plate is divided into multiple field plates (first field plate and second field plate) separated by an insulating spacer. This segmentation distributes the electric field more evenly, reducing peak electric fields and preventing electron trapping while maintaining high breakdown voltage capability
Solution Approach 2:
An insulating spacer is introduced as an intermediary element between the first and second field plates. This spacer electrically isolates the two field plates while allowing them to work together in reducing peak electric fields and enhancing breakdown voltage without causing electron trapping
2Speed
If the gate length is reduced to improve switching speed, then the device operates at higher frequencies, but the breakdown voltage decreases and electric field concentration increases
Solution Approach 1:
The field plate structure is segmented into multiple sections that can be optimized independently. This allows the gate length to be reduced for high-speed operation while the distributed field plates maintain adequate breakdown voltage by reducing electric field concentration at any single point
3Power
If higher current density is achieved by reducing on resistance, then power performance improves, but heat dissipation becomes more challenging
Solution Approach 1:
The multiple field plate structure enables better current distribution across the device, allowing higher current density to be achieved more uniformly. This improves power performance while the more uniform current distribution helps manage heat generation and dissipation more effectively
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multiple field plate transistor design achieves blocking voltages of at least 600V with low on resistance, supporting high current densities and reducing leakage currents, thus enhancing the performance and reliability of power switching devices.
Implementation Method 1
The first field plate and the second field plate reduce peak electric fields in the transistor
Implementation Method 2
The first spacer layer electrically isolates the first field plate from the active region, and the second spacer layer electrically isolates the second field plate from the active region
Implementation Method 3
a gate between the source and drain electrodes for modulating electric fields within the active region
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
A multiple field plate transistor includes an active region, with a source, a drain, and a gate. A first spacer layer is over the active region between the source and the gate and a second spacer layer over the active region between the drain and the gate. A first field plate on the first spacer layer is connected to the gate. A second field plate on the second spacer layer is connected to the gate. A third spacer layer is on the first spacer layer, the second spacer layer, the first field plate, the gate, and the second field plate, with a third field plate on the third spacer lay and connected to the source. The transistor exhibits a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 5.0 mΩ-cm2, of at least 600 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 5.3 mΩ-cm2, of at least 900 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 6.6 mΩ-cm2, or a blocking voltage of at least 900 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 7.0 mΩ-cm2.