GaN Transistor 3D Folded Channel for Current Scaling
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Solution Overview
Problem
GaN-based transistors face issues with poor current scaling and current collapse due to limited surface conduction and wasted area in lateral configurations, as well as high on-state resistance, which are exacerbated by surface and bulk traps under high voltage stress.
Innovation Solution
A lateral III-nitride semiconductor heterojunction power device with a three-dimensional geometry is introduced, featuring vertical and lateral channels formed by two-dimensional carrier gases within trenches and mesa regions, which increase the effective current conduction area and reduce on-state resistance by self-shielding from traps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a lateral configuration with two-dimensional carrier gas is used, then the device structure is simple and easy to manufacture, but the current scaling is poor and the effective conduction area is limited
Solution Approach 1:
The patent transitions from a two-dimensional lateral channel configuration to a three-dimensional folded channel geometry. The channel is configured to extend in multiple dimensions including vertical portions and lateral portions, effectively increasing the conduction area without proportionally increasing the device footprint. This dimensional transformation allows the channel to utilize both lateral and vertical spaces, achieving better current scaling while maintaining manufacturing feasibility through extended hetero-structure formation.
2Productivity
If a larger surface area is used for current conduction, then the current density increases, but the device area waste increases in lateral configurations
Solution Approach 1:
The patent employs a folded channel geometry that extends vertically and laterally, allowing the channel to achieve larger effective conduction area within a compact device footprint. The vertical portions of the channel utilize the third dimension (depth) to increase conduction area without expanding the lateral device footprint, thereby improving current density while minimizing device area waste.
Solution Approach 2:
The channel structure is nested within a folded geometry that utilizes both lateral and vertical spaces efficiently. The hetero-structure channels are configured to fold back on themselves, creating a compact nested arrangement that maximizes the conduction area within the available device volume, achieving high current density without proportional increase in device area.
3Strength
If high voltage stress is applied, then the breakdown voltage capability is improved, but surface and bulk traps are activated causing current collapse
Solution Approach 1:
The patent utilizes vertical portions of the folded channel that extend into the bulk material, allowing the channel to access higher quality regions away from surface traps. The vertical extension enables the channel to maintain stable conduction by utilizing deeper hetero-structure regions that are less susceptible to surface trap effects, thereby improving current stability under high voltage stress.
Solution Approach 2:
The patent creates different channel regions with different qualities - lateral portions near the surface and vertical portions extending deeper into the bulk. The vertical portions utilize regions with fewer surface traps and better material quality, providing stable conduction paths that are less affected by trap activation under high voltage stress, thereby maintaining current stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The three-dimensional geometry significantly enhances current density and stability by increasing the effective area for current flow, reducing on-state resistance, and minimizing the impact of surface and bulk traps, thereby improving the long-term reliability of GaN-based transistors.
Implementation Method 1
a two-dimensional carrier gas confined at the AlGaN/GaN interface
Implementation Method 2
their piezoelectric nature which gives very high charge density (e.g. 1e13 cm−2) confined at the AlGaN/GaN interface
Implementation Method 3
A Schottky gate contact placed on top of the hetero-structure along the source-to-drain distance modulates the charge in the channel
Implementation Method 4
a two-dimensional carrier gas constituting a channel of the transistor has a three-dimensional folded geometry
Implementation Method 5
vertical and lateral channels formed by two-dimensional carrier gases within trenches and mesa regions, which increase the effective current conduction area and reduce on-state resistance by self-shielding from traps
Data Source
AI summary
A heterojunction power device includes a substrate; a III-nitride semiconductor region over the substrate; a source operatively connected to the semiconductor region; a drain operatively connected to the semiconductor region; a gate between the source and drain and over the semiconductor region. The source is in contact with a first portion located between the source and gate and having a two dimensional carrier gas. The drain is in contact with a second portion located between the drain and gate and having a two dimensional carrier gas. At least one of the first and second portions has a trench having vertical sidewalls and formed within the semiconductor region; mesa regions extend away from each sidewall of the trench. The two dimensional carrier gas is located alongside the mesa regions and the trench. At least one of the source and drain is in contact with the respective two dimensional carrier gas.