GaN Transistor Gate Dielectric Stack for Leakage Reduction
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Solution Overview
Problem
Group IIIA-N transistors, such as GaN FETs, face high gate leakage issues due to high interface trap state densities when using SiN or SiON gate dielectrics, which limits their performance and reliability, particularly in high-power and high-frequency applications.
Innovation Solution
A multi-layer gate dielectric stack is fabricated by thermally oxidizing the Group IIIA-N surface to form a first oxide layer, followed by depositing a second dielectric layer of silicon nitride or silicon oxynitride, and forming a gate electrode, with optional annealing steps to reduce gate leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SiN or SiON gate dielectrics are used on Group IIIA-N materials, then the device structure is simple and manufacturing is easier, but gate leakage is high due to high interface trap state densities
Solution Approach 1:
The gate dielectric is divided into multiple layers: a first dielectric layer (SiN or SiON) deposited directly on the Group IIIA-N layer, and a second dielectric layer (oxide material) deposited on top of the first layer. This segmentation allows each layer to perform different functions - the first layer provides good interface characteristics while the second layer provides high breakdown voltage, thereby reducing overall gate leakage without requiring complex processing
Solution Approach 2:
The patent uses a composite gate dielectric structure combining two different dielectric materials (SiN/SiON and oxide material) with complementary properties. The SiN/SiON layer provides low interface trap density while the oxide layer provides high electrical breakdown strength, creating a composite structure that achieves both low gate leakage and high reliability
2Reliability
If thermal treatments are applied before and after gate dielectric deposition, then interface trap states are reduced somewhat, but gate leakage reduction is not sufficient for high-power applications
Solution Approach 1:
The first dielectric layer (SiN or SiON) is deposited directly on the Group IIIA-N layer before any thermal treatments, serving as an interface protection layer that prevents excessive trap state formation during subsequent processing. This preliminary action eliminates the need for complex pre-deposition thermal treatments while maintaining good interface characteristics
Solution Approach 2:
The first dielectric layer acts as an intermediary between the Group IIIA-N layer and the second oxide dielectric layer. It provides a stable interface that reduces trap state formation during the deposition and thermal treatment of the second layer, thereby reducing gate leakage without requiring extensive thermal processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-layer gate dielectric stack significantly reduces gate leakage by about one order of magnitude, enhancing the performance and reliability of Group IIIA-N transistors for high-power applications.
Implementation Method 1
A multi-layer gate dielectric stack is fabricated by thermally oxidizing the Group IIIA-N surface to form a first oxide layer, followed by depositing a second dielectric layer of silicon nitride or silicon oxynitride
Implementation Method 2
thermally oxidizing the surface of a Group IIIA-N layer that is on a substrate to form a first dielectric layer comprising an oxide material
Data Source
AI summary
A method of fabricating a gate stack for a power transistor device includes thermally oxidizing a surface of a Group IIIA-N layer on a substrate to form a first dielectric layer of an oxide material that is >5 A thick. A second dielectric layer being silicon nitride or silicon oxynitride is deposited on the first dielectric layer. A metal gate electrode is formed on the second dielectric layer.