GaN Enhancement Mode Transistor Gate Protection Circuit
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Solution Overview
Problem
Enhancement mode GaN FETs with semiconductor gates are susceptible to excessive gate leakage current and gate dielectric breakdown when overbiased, while those with insulated gates face dielectric breakdown.
Innovation Solution
A semiconductor device comprising an enhancement mode GaN FET with a p-type semiconductor gate or insulated gate electrically coupled in series with a depletion mode GaN FET, where the gate node of the depletion mode FET is connected to the source node of the enhancement mode FET, allowing for controlled gate biasing to prevent excessive voltage drops and maintain pinch-off voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If enhancement mode GaN FET with semiconductor gate is used, then high bandgap and high thermal conductivity are achieved, but excessive gate leakage current occurs when gate is overbiased
Solution Approach 1:
A depletion mode GaN FET is introduced as an intermediary component between the gate terminal and the enhancement mode GaN FET gate. This intermediate device limits the gate-source voltage to a maximum value (Vds_max of the depletion mode FET) regardless of the voltage applied to the gate terminal, thereby preventing excessive gate leakage current while preserving the thermal conductivity benefits of the enhancement mode device.
2Ease of operation
If enhancement mode GaN FET with insulated gate is used, then gate control is improved, but gate dielectric breakdown occurs when gate is overbiased
Solution Approach 1:
The depletion mode GaN FET is connected in series with the gate terminal beforehand to provide voltage protection. This series connection acts as a protective cushion that limits the maximum gate-source voltage to Vds_max of the depletion mode FET, preventing gate dielectric breakdown in the enhancement mode FET before it can occur during operation.
3Power
If gate bias is increased to improve switching performance, then power switch capability is enhanced, but gate leakage current and dielectric breakdown risk increase
Solution Approach 1:
The depletion mode GaN FET provides automatic feedback voltage limiting to the enhancement mode FET gate. When the gate-source voltage of the enhancement mode FET reaches Vds_max of the depletion mode FET, the depletion mode device enters saturation and maintains a constant voltage drop, automatically regulating the gate voltage and preventing overbiasing while allowing full power switch capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces excessive current draw and prevents gate dielectric breakdown by maintaining the gate bias below the maximum desired level, ensuring reliable operation of the semiconductor device.
Implementation Method 1
A high gate bias which is above the maximum desired gate-source bias may be applied to the gate terminal of the semiconductor device; the high gate bias causes the depletion mode GaN FET to go into pinch-off mode so that the source node of the depletion mode GaN FET is maintained at the pinch-off voltage
Data Source
AI summary
A semiconductor device includes an enhancement mode GaN FET with a depletion mode GaN FET electrically coupled in series between a gate node of the enhancement mode GaN FET and a gate terminal of the semiconductor device. A gate node of the depletion mode GaN FET is electrically coupled to a source node of the enhancement mode GaN FET. A source node of said enhancement mode GaN FET is electrically coupled to a source terminal of the semiconductor device, a drain node of the enhancement mode GaN FET is electrically coupled to a drain terminal of said semiconductor device, and a drain node of the depletion mode GaN FET is electrically coupled to a gate terminal of the semiconductor device.