GaN Transistor with Segmented Gate Regions for Linearity
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Solution Overview
Problem
Conventional GaN transistors suffer from poor linearity performance due to non-linear DC-transconductance behavior around the threshold voltage, leading to intermodulation distortion and high power consumption in RF power amplifiers, especially when driven near saturation levels.
Innovation Solution
The development of a transistor with multiple gate-controlled regions having different threshold voltages, achieved through varying the threshold voltage in discrete or continuous regions, allowing for the creation of sub-transistors in parallel with offset threshold voltages to reduce the second derivative of transconductance (g″m), thereby improving linearity and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional GaN transistors are used, then high power output is achieved, but linearity performance deteriorates due to non-linear DC-transconductance behavior around threshold voltage
Solution Approach 1:
The transistor channel is divided into multiple gate-controlled regions with different threshold voltages. Each region is independently controlled by its own gate, allowing the transistor to process different portions of the input signal with optimized threshold characteristics, thereby improving overall linearity while maintaining high power output capability
Solution Approach 2:
Different regions of the transistor are engineered with distinct threshold voltages tailored to specific signal portions. Regions with lower threshold voltages handle weaker signal components while regions with higher threshold voltages handle stronger components, creating local optimization that reduces intermodulation distortion and improves linearity across the full signal range
2Use of energy by moving object
If transistors are driven near saturation levels, then power efficiency is improved, but intermodulation distortion increases due to non-linear transconductance
Solution Approach 1:
The transistor is segmented into multiple gate-controlled regions that can be independently biased. This allows different regions to operate at different points on their transconductance curves, with some regions operating near saturation for efficiency while others operate in more linear regions, thereby reducing intermodulation distortion while maintaining overall power efficiency
Solution Approach 2:
The threshold voltage parameter is varied across different gate-controlled regions to optimize the trade-off between power efficiency and linearity. By adjusting threshold voltages, the transistor can maintain operation near saturation for efficiency while the distributed threshold values prevent the strong non-linearities that cause intermodulation distortion
3Measurement precision
If multiple gate-controlled regions with different threshold voltages are created, then linearity is improved by reducing g''m, but device complexity increases
Solution Approach 1:
Multiple gate-controlled regions are merged into a single integrated transistor structure with shared source and drain regions. The gates are positioned adjacent to each other along the channel, creating a unified device that achieves improved linearity through threshold voltage diversity without requiring separate transistor structures, thereby limiting the increase in device complexity
Data Source
AI summary
A transistor includes a first gate-controlled region having a first threshold voltage and a second gate-controlled region in parallel with the first gate-controlled region. The second gate-controlled region has a second threshold voltage different form the first threshold voltage.