GaN Transistor Stacked Architecture for Parasitic Reduction
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Solution Overview
Problem
Existing semiconductor technologies face challenges in extending transition frequencies for millimeter wave and beyond radio frequency applications due to interconnect parasitics effects, particularly in the millimeter wave and terahertz regimes, which limit the frequency and power capabilities of devices like GaN HEMTs.
Innovation Solution
A transition frequency multiplier semiconductor device is designed with a Darlington-like configuration, featuring separate channel regions and gate regions, along with conductive interconnects and resistors to minimize parasitics, allowing for increased transition frequencies and breakdown voltages through improved device architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multi-transistor circuit topologies (Darlington-pair, cascode, multi-stacked transistors) are used to improve fT-breakdown product, then transition frequency and breakdown voltage are improved, but interconnect parasitics effects increase especially in mmW and THz regimes
Solution Approach 1:
The device is segmented into multiple independent transistor units (first transistor and second transistor) with separate channel regions and gate regions. This segmentation allows each transistor to operate independently while contributing to the overall fT-breakdown product, reducing the cumulative parasitic effects that would occur in traditional multi-transistor topologies.
Solution Approach 2:
The patent transitions from planar interconnect arrangements to a vertical stacking architecture where transistors are arranged in the vertical dimension. The first transistor and second transistor are stacked with their channel regions separated by an inactive channel region, allowing direct coupling while minimizing horizontal interconnect parasitics.
2Power
If traditional multi-transistor topologies are used, then voltage operation and fT multiplication are improved, but device complexity increases
Solution Approach 1:
The patent merges multiple transistor functions into a single integrated device structure. The first transistor and second transistor are combined in a stacked configuration sharing common elements, achieving voltage operation and fT multiplication without the complexity of separate multi-transistor circuits. The inactive channel region acts as an integrated isolation element between the two transistors.
3Speed
If short gate-length enhancement mode GaN transistor technology is used, then electron velocity and energy band-gap are improved, but transition frequency extension is limited by parasitics
Solution Approach 1:
The patent utilizes the vertical dimension to stack transistors with short gate lengths, allowing the high electron velocity and wide energy band-gap properties of GaN to be fully exploited. The vertical arrangement minimizes parasitic inductance and capacitance that would otherwise limit frequency extension, enabling the intrinsic high-speed properties of GaN to translate into higher transition frequencies.
Data Source
AI summary
A transition frequency multiplier semiconductor device having a first source region, a second source region, and a common drain region is disclosed. A first channel region is located between the first source region and the common drain region, and a second channel region is located between the second source region and the common drain region. A first gate region is located within the first channel region to control current flow between the first source region and the common drain region, while a second gate region is located within the second channel region to control current flow between the second source region and the common drain region. An inactive channel region is located between the first channel region and the second channel region such that the first channel region is electrically isolated from the second channel region. A conductive interconnect couples the first source region to the second gate region.