GaN Power Transistor Integration With Monolithic Start-Up Circuit
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Solution Overview
Problem
Current power semiconductor devices face challenges in integrating start-up components with main power transistors due to compatibility issues between Schottky gate and pGaN gate technologies, limiting threshold control and efficiency in switch mode power supplies.
Innovation Solution
A monolithically integrated GaN-based device is proposed, featuring a normally-off enhancement mode field-effect transistor as the main power switch and a high voltage, normally-on depletion mode transistor as a start-up component, allowing for reduced system size and costs, improved performance, and energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Schottky gate technology is used for start-up components, then device compatibility is improved, but threshold control is limited
Solution Approach 1:
The patent segments the gate structure into two distinct types: Schottky gates for the start-up transistor and pGaN gates for the main power transistor. This segmentation allows each transistor type to be optimized for its specific function while being fabricated in the same process, resolving the contradiction between compatibility and threshold control.
Solution Approach 2:
Different gate regions are assigned different materials and structures tailored to their specific requirements. The Schottky gate region provides excellent compatibility for the start-up component, while the pGaN gate region enables precise threshold control for the main power transistor, achieving local optimization throughout the device.
2Reliability
If separate fabrication processes are used for enhancement and depletion mode transistors, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the fabrication processes for enhancement mode and depletion mode transistors into a single unified process flow. Both transistor types are formed in the same AlGaN/GaN heterostructure using the same epitaxial growth and photolithography steps, eliminating the need for separate fabrication processes while maintaining device performance.
Solution Approach 2:
The unified fabrication process is designed to be universal, capable of producing both enhancement mode and depletion mode transistors with the same equipment and material layers. This multi-functional approach simplifies manufacturing while ensuring consistent device performance across different transistor types.
3Adaptability or versatility
If discrete components are used for start-up circuit, then design flexibility is improved, but system size and costs increase
Solution Approach 1:
The patent merges the start-up circuit functionality directly into the power device structure by integrating the start-up transistor alongside the main power transistor in a single monolithic device. This integration eliminates the need for separate discrete components, reducing system size while maintaining design flexibility through independent gate control.
Solution Approach 2:
The start-up transistor is nested within the same device footprint as the main power transistor, with both transistors sharing the same AlGaN/GaN heterostructure layers. This nested arrangement allows the start-up circuit to be embedded within the power device, minimizing overall system size and reducing component count.
Data Source
AI summary
An Ill-nitride semiconductor based heterojunction power device is disclosed and includes a first and second heterojunction transistors formed on a substrate. The first and second heterojunction transistors include first and second Ill-nitride semiconductor regions formed over the substrate. The first Ill-nitride semiconductor region includes a first heterojunction, a first terminal connected to the first Ill-nitride semiconductor region, a second terminal laterally spaced from the first terminal and connected to the first Ill-nitride semiconductor region, and a first gate region over the first Ill-nitride semiconductor region between the first and second terminals. The second Ill-nitride semiconductor region includes a second heterojunction, a third terminal connected to the second Ill-nitride semiconductor region, a fourth terminal laterally spaced from the third terminal and connected to the second Ill-nitride semiconductor region, first highly doped semiconductor regions of a first conductivity type formed over the second Ill-nitride semiconductor region.