GaN Trap-Rich Region Mitigates Parasitic Conduction
Solution Overview
Problem
Gallium nitride electronic devices on high resistivity silicon substrates form a high conductivity inversion layer that electromagnetically couples with circuits, causing power loss and noise due to parasitic conduction and capacitive coupling, which affects RF performance.
Innovation Solution
A method is developed to create a trap rich region at the silicon-gallium nitride interface by cold-melting a thin layer of the silicon substrate using a short laser pulse, immobilizing charge carriers and mitigating the parasitic impact of the inversion layer, which involves forming a buffer layer and extending the trap region into the silicon substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gallium nitride layer is epitaxially grown on a high resistivity silicon substrate, then the device structure is formed, but a high conductivity inversion layer forms at the interface causing parasitic conduction and capacitive coupling
Solution Approach 1:
The patent extracts and removes the harmful inversion layer from the silicon substrate surface through chemical etching processes. The etch selectively removes the contaminated surface layer where the inversion layer forms, eliminating the source of parasitic conduction while preserving the bulk silicon substrate properties.
Solution Approach 2:
The patent applies local quality by creating a differentiated surface treatment: the silicon substrate surface is chemically etched to remove the inversion layer at the interface region, while the bulk substrate maintains its high resistivity. This localized modification eliminates parasitic effects only where needed at the GaN/Si interface.
2Loss of energy
If the inversion layer is present at the GaN/Si interface, then the device structure is complete, but power loss and noise increase due to electromagnetic coupling with circuits
Solution Approach 1:
The harmful electromagnetic coupling effect is eliminated by extracting and removing the inversion layer that causes it. The chemical etching process removes the conductive layer at the interface, thereby eliminating the source of parasitic electromagnetic coupling between the GaN device and the silicon substrate.
Solution Approach 2:
The solution applies local quality by treating only the interface region where electromagnetic coupling occurs. The chemical etch selectively modifies the surface layer at the GaN/Si interface to remove the inversion layer, while leaving the bulk substrate unchanged, thus reducing power loss and noise only where the harmful coupling occurs.
3Manufacturing precision
If high temperatures are applied during epitaxial growth, then the gallium nitride layer is formed, but the temperature causes diffusion of Al and Ga into silicon doping the substrate and decreasing resistivity
Solution Approach 1:
The patent applies preliminary action by performing chemical etching of the silicon substrate surface before epitaxial growth. This pre-treatment removes the contaminated surface layer that would otherwise be doped during high-temperature growth, preventing the formation of the inversion layer while allowing the subsequent epitaxial process to proceed at necessary high temperatures.
Solution Approach 2:
The chemical etching process provides preliminary anti-action by removing the surface layer that would become doped during epitaxial growth. This preemptive removal prevents the harmful diffusion of Al and Ga into the silicon substrate, counteracting the unwanted doping effect before it can occur during the high-temperature epitaxial process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves RF performance by eliminating the inversion layer, reducing power loss and noise, and increasing the resistivity of the silicon substrate, enabling gallium nitride devices to operate effectively up to 60 GHz or more for power and RF electronics.
Implementation Method 1
A method is developed to create a trap rich region at the silicon-gallium nitride interface by cold-melting a thin layer of the silicon substrate using a short laser pulse
Implementation Method 2
cold-melting a thin layer of the silicon substrate using a short laser pulse
Implementation Method 3
the disordering of the lattice generates traps that prevent the charges from moving freely and would destroy the inversion layer
Implementation Method 4
The buffer layer may be epitaxially grown using high temperatures in excess of 1000 degrees Celsius
Implementation Method 5
The Aluminum Nitride may diffuse and dope a thin layer of the silicon reducing the resistivity of the silicon in that layer (forming an inversion layer)
Data Source
AI summary
A method cold-melts a high conductivity region between a high-resistivity silicon substrate and a gallium-nitride layer to form a trap rich region that substantially immobilizes charge carriers in that region. Such a process should substantially mitigate the parasitic impact of that region on circuits formed at least in part by the gallium-nitride layer.