GaN-on-Si Trench Cladding for Dicing Crack Mitigation
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Solution Overview
Problem
High voltage and high current lateral GaN power transistors on silicon substrates face issues with cracking and defect creation during wafer dicing due to thermal and lattice mismatch, leading to reliability concerns and reduced yield.
Innovation Solution
A trench structure is formed around the periphery of each GaN die, extending through the interconnect layers and into the silicon substrate, with a trench cladding of dielectric and metal layers to protect the GaN epi-layers and reduce dicing-induced damage, and optionally, intra-die trenches provide stress relief across the die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a thicker GaN epi-layer stack is used to provide increased breakdown voltage for high voltage devices, then the breakdown voltage capability is improved, but the thermal and lattice mismatch between GaN and silicon substrate causes significant interlayer stresses and wafer bowing, leading to cracking during fabrication and reliability issues
Solution Approach 1:
The patent segments the GaN epi-layer stack into multiple thinner layers (e.g., alternating GaN and AlN layers) rather than using a single thick GaN layer. This segmentation reduces the cumulative stress from thermal and lattice mismatch while maintaining the required breakdown voltage through the combined thickness of the segmented structure, thereby preventing cracking during fabrication.
Solution Approach 2:
The patent changes the structural parameters of the epi-layer stack by introducing intermediate layers (such as AlN or AlGaN) with different material properties. These intermediate layers have lower thermal expansion coefficients closer to silicon, reducing the thermal mismatch parameter. The layered structure modifies the stress distribution parameter to prevent cracking while achieving the required voltage blocking capability.
2Productivity
If conventional mechanical sawing is used for wafer dicing to separate individual die, then the dicing process is simple and fast, but it causes dicing damage that seeds cracks in the GaN epi-layers, leading to reliability issues
Solution Approach 1:
The patent extracts the problematic mechanical cutting step from the dicing process by introducing a pre-formed trench structure that physically separates the GaN epi-layer from the substrate at the dicing location. This extraction eliminates the direct mechanical contact between the saw blade and the GaN layer, preventing crack seeding while maintaining efficient dicing throughput.
Solution Approach 2:
The patent performs preliminary action by forming protective trench structures and stress relief features in the substrate before the dicing process. These pre-formed structures create stress-free zones and physical barriers that prevent crack propagation during subsequent mechanical sawing, allowing fast dicing without compromising reliability.
3Object-affected harmful factors
If laser grooving is used for wafer dicing to avoid mechanical damage, then mechanical damage is reduced, but it creates surface damage and defects in the region of the substrate/GaN epi-layer interface, requiring additional etching or cleaning steps
Solution Approach 1:
The patent converts the potentially harmful laser-induced surface damage into a beneficial pre-formed trench structure. By carefully controlling the laser grooving process, the damaged region is confined to a specific trench area that is then filled with protective material. This transforms what would be a defect into a protective feature that prevents crack propagation while eliminating the need for additional cleaning steps.
4Reliability
If intermediate layers are added to reduce thermal and lattice mismatch, then the stress and wafer bowing are reduced, but the fabrication process becomes more complex and the number of fabrication steps increases
Solution Approach 1:
The patent merges the functions of multiple intermediate layers into a single integrated buffer structure that performs both stress reduction and lattice matching simultaneously. By combining the buffer layer and barrier layer functions into one optimized structure, the number of separate fabrication steps is reduced while maintaining the stability benefits of having intermediate layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The trench structure effectively reduces the risk of cracking and defect propagation during dicing, enhancing the yield and reliability of GaN power devices by mitigating interlayer stresses and protecting the active regions from mechanical and electro-migration damage.
Implementation Method 1
a trench cladding comprising at least one dielectric layer and optionally a metal layer, the trench cladding extending over inner sidewalls of the trench and sealing exposed surfaces of layers of the interconnect structure, layers of the GaN epi-layer stack and the interface region of the GaN epi-layers and the silicon substrate
Implementation Method 2
the thermal and lattice mismatch and the resulting interlayer stresses/strains between the GaN epi-layers and the silicon substrate introduces defects
Data Source
AI summary
A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.