GaN Vertical Trench Gate Structure With Precise Depth Control
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Solution Overview
Problem
Existing manufacturing processes for vertical devices, particularly the gate structure part, lack controllability, leading to deviations in performance from pre-designed specifications.
Innovation Solution
A method involving a GaN-based semiconductor substrate etched to form a trench, where a P-type semiconductor layer and an N-type semiconductor layer are sequentially formed on the trench and front surface, planarized, and used to create a gate structure, source electrode, and drain electrode, avoiding etching of these layers to enhance control over the gate structure's depth and precision in performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing manufacturing processes are used to form vertical devices, then the devices can be manufactured, but the gate structure performance deviates from pre-designed specifications due to poor controllability
Solution Approach 1:
The patent forms the N-type semiconductor layer and P-type semiconductor layer in advance before forming the gate structure. The N-type layer is deposited to fill the trench and extend onto the front surface, then the P-type layer is deposited to fill the trench partially. This preliminary formation of doped regions provides a stable foundation for subsequent gate structure fabrication, ensuring that the gate structure can be precisely positioned and that its performance matches design specifications.
Solution Approach 2:
The patent applies different doping types and concentrations to different regions: the N-type semiconductor layer is formed on the front surface and extends into the trench, while the P-type semiconductor layer fills the trench partially. This creates locally optimized regions with specific electrical properties - the N-type region provides electron supply and the P-type region creates the depletion layer. This local differentiation enables precise control over the gate structure's electrical characteristics and performance.
2Manufacturing precision
If the trench is fully filled with semiconductor layers, then the structure is complete, but the gate structure control capability cannot be precisely controlled due to etching depth difficulties
Solution Approach 1:
The patent forms the N-type and P-type semiconductor layers before forming the gate structure, establishing the vertical profile and doping distribution in advance. The N-type layer is deposited to a thickness that extends beyond the trench depth, and the P-type layer is deposited to partially fill the trench. This preliminary action creates a well-defined substrate structure that simplifies subsequent gate formation and ensures precise depth control without requiring complex etching processes.
Solution Approach 2:
Instead of forming the gate structure first and then creating doped regions through etching, the patent inverts the sequence by forming the doped semiconductor layers first and then creating the gate structure on top. This inversion eliminates the need for precise etching depth control to define the gate structure's vertical position, as the doped layers already provide the necessary vertical profile and electrical characteristics.
3Reliability
If ion doping is performed with existing methods, then doping can be achieved, but punch-through effects occur and current capacity is limited
Solution Approach 1:
The patent creates distinct N-type and P-type doped regions with specific spatial distributions. The N-type layer is formed on the front surface and extends into the trench, while the P-type layer fills the trench partially, creating a well-defined junction. This local differentiation of doping types and concentrations prevents excessive depletion layer extension that would cause punch-through effects, while optimizing the electrical characteristics for enhanced current capacity and device reliability.
Solution Approach 2:
The P-type semiconductor layer acts as an intermediary between the N-type layer and the gate structure. It creates a depletion layer that modulates the electrical field distribution, preventing direct interaction between the N-type source/drain regions that would cause punch-through effects. This intermediary P-type region provides controlled electrical isolation while allowing the gate structure to effectively modulate current flow, thereby enhancing device reliability and current capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for precise control over the performance of vertical devices by preventing deviations in the gate structure's control capability, enabling precise ion doping and reducing the risk of punch-through effects, while increasing current capacity and compatibility with existing processes.
Implementation Method 1
the N-type semiconductor layer and the P-type semiconductor layer are planarized
Data Source
AI summary
The present application provides methods for manufacturing a vertical device. To begin with, a GaN-based semiconductor substrate is etched from a front surface to form a trench. Then, a P-type semiconductor layer and an N-type semiconductor layer are sequentially formed on a bottom wall and side walls of the trench and the front surface of the semiconductor substrate. The trench is partially filled with the P-type semiconductor layer. Thereafter, the N-type semiconductor layer and the P-type semiconductor layer are planarized, and the P-type semiconductor layer and the N-type semiconductor layer in the trench are retained. Next, a gate structure is formed at a gate area of the front surface of the semiconductor substrate, a source electrode is formed on two sides of the gate structure, and a drain electrode is formed on a rear surface of the semiconductor substrate respectively.