GaN Trench Gate Semiconductor Device with Convex P-Type Layer
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Solution Overview
Problem
Trench gate semiconductor structures face challenges in forming p-type semiconductors, particularly in group-III nitride semiconductors like gallium nitride, due to difficulties with ion implantation, leading to deteriorated electrical properties and increased manufacturing complexity, with issues such as increased on resistance and potential crowding.
Innovation Solution
A semiconductor device design featuring a p-type semiconductor layer with projections and a trench structure that relieves potential crowding, formed without ion implantation, using crystal growth and dry etching, to improve electrical properties and reduce manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If ion implantation is used to form p-type semiconductor in trench gate structure, then breakdown voltage is improved, but it is not applicable to group-III nitride semiconductors and manufacturing complexity increases
Solution Approach 1:
The invention changes the doping method from ion implantation to in-situ doped crystal growth, adapting the manufacturing process to suit group-III nitride semiconductors while maintaining the breakdown voltage improvement effect through the formation of p-type semiconductor regions at the trench bottom
Solution Approach 2:
The invention replaces the mechanical ion implantation process with a chemical crystal growth process, substituting a physical method with a chemical method that is more suitable for group-III nitride semiconductors and reduces manufacturing complexity
2Strength
If selective regrowth is used to form p-type semiconductor, then breakdown voltage is improved, but manufacturing process becomes complicated
Solution Approach 1:
The invention extracts and eliminates the masking step from the selective regrowth process, using in-situ doped crystal growth to directly form p-type semiconductor regions without requiring complex mask patterns and selective growth procedures
Solution Approach 2:
The in-situ doped crystal growth method serves multiple functions: it forms the p-type semiconductor regions, defines the trench bottom structure, and improves breakdown voltage, replacing the multiple separate steps of masking, selective regrowth, and doping
3Strength
If p-type semiconductor is formed by selective regrowth, then breakdown voltage is improved, but electrical properties deteriorate due to dopant diffusion
Solution Approach 1:
The invention performs doping during the crystal growth process itself, preliminarily incorporating dopants into the p-type semiconductor regions before subsequent processing steps, thereby preventing dopant diffusion into the n-type semiconductor layer and preserving electrical properties
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively improves the electrical properties and breakdown voltage of semiconductor devices, particularly those with gallium nitride, by reducing on resistance and potential crowding, while simplifying the manufacturing process.
Implementation Method 1
relieves the potential crowding on the bottom of the trench in the trench gate structure
Implementation Method 2
a first interface and a second interface that forms an upper surface of a convex protruded from the first interface
Data Source
AI summary
A semiconductor device includes a first n-type semiconductor layer, a p-type semiconductor layer, a second n-type semiconductor layer and a trench. The first n-type semiconductor layer includes a first interface and a second interface. The second interface forms an upper surface of a convex protruded from the first interface. The p-type semiconductor layer is stacked on the first n-type semiconductor layer and includes a first region stacked on the first interface and a second region stacked on the second interface. The first region is uniformly continuous with the second region. The second n-type semiconductor layer is stacked on the p-type semiconductor layer. The trench is depressed from the second n-type semiconductor layer through the p-type semiconductor layer into the convex of the first n-type semiconductor layer.


