GaN Lateral-Conduction Metallization Layout for Electromigration Control
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Solution Overview
Problem
The current rating of lateral GaN power devices is limited by the capability of metallizations to drive high currents due to electromigration and self-heating, which is exacerbated by the need for complex embedded systems and packaging processes, and classical interdigitated structures are not suitable for high-current GaN power devices.
Innovation Solution
The solution involves properly shaping on-die metallizations with variable width metal buses that follow the current density gradient, using trapezoidal-shaped subregions and optimizing the geometry to minimize on-chip area while avoiding electromigration, without affecting the specific on-resistance of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wide metal interconnections are used to avoid electromigration failure, then current carrying capability is improved, but die area increases
Solution Approach 1:
The patent applies local quality by varying the metal interconnection width according to the local current density requirements. The metal traces are wider in regions with higher current density and narrower in regions with lower current density, optimizing both electromigration resistance and area utilization. This is achieved through a systematic approach where the width of each metal segment is calculated based on the current it carries and the maximum allowable current density for electromigration prevention.
Solution Approach 2:
The patent implements dynamics by transitioning from fixed-width metal interconnections to variable-width metal interconnections. The width of the metal traces dynamically adapts to the current density distribution across the device, allowing the interconnection structure to optimize performance based on operational requirements while minimizing area.
2Reliability
If thick metallizations are used to drive high currents, then current rating is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the metal interconnection into multiple segments or sections, each with optimized width tailored to the local current requirements. This segmentation allows the device to achieve high current rating capabilities without requiring uniformly thick metallizations across the entire device, thereby reducing overall complexity while maintaining high current performance in critical regions.
3Reliability
If large die area is occupied by pads and interconnections, then current carrying capability is improved, but power density decreases
Solution Approach 1:
The patent applies local quality by concentrating the metal interconnection width optimization in regions where high current density is required, rather than uniformly increasing the size of all pads and interconnections. This allows the device to maintain high current carrying capability in critical areas while minimizing the overall die area consumed by interconnections, thereby preserving power density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the safe carrying of high currents (>10 A) within integrated devices without complex post-processing or packaging, maintaining low specific on-resistance and ensuring high FE-BE compatibility, thus enhancing current rating without increasing the device's area or complexity.
Implementation Method 1
The current is distributed to a plurality of drain and source fingers through a plurality of metal buses formed in a highest on-die metallization level
Implementation Method 2
properly shaping on-die metallizations with variable width metal buses that follow the current density gradient
Implementation Method 3
The metal layers are electrically insulated from one another by a dielectric or insulating layer
Data Source
AI summary
An electronic device, comprising plurality of source metal strips in a first metal level; a plurality of drain metal strips in the first metal level; a source metal bus in a second metal level above the first metal level; a drain metal bus, in the second metal level; a source pad, coupled to the source metal bus; and a drain pad, coupled to the drain metal bus. The source metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the first conductive pad; the drain metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the second conductive pad. The first and second subregions are interdigitated.