GaN Vertical MESFET Self-Aligned Channel Design
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Solution Overview
Problem
Conventional methods for manufacturing power electronic devices, such as MESFETs, face limitations in achieving high-voltage operation and low resistance due to substrate mismatch and high defect densities, which restrict the thickness and quality of GaN layers, leading to suboptimal performance and reliability.
Innovation Solution
The use of homoepitaxial GaN layers on bulk GaN substrates allows for the fabrication of vertical metal-semiconductor field-effect transistors (MESFETs) with thicker semiconductor layers, enabling higher voltage operation and lower resistance, along with the implementation of Schottky metal gates instead of semiconductor gates, facilitating improved power density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional substrate mismatch methods are used, then manufacturing process is simple, but GaN layer thickness is limited and defect density is high
Solution Approach 1:
The patent employs homoepitaxial growth where GaN layers are grown on GaN substrates, ensuring material homogeneity and lattice matching. This eliminates substrate mismatch issues, allows for thicker layers with lower defect densities, and maintains manufacturing feasibility through established epitaxial processes.
2Power
If thicker GaN layers are used, then voltage operation and power density improve, but manufacturing complexity increases
Solution Approach 1:
The patent segments the device into distinct functional regions including drift region, barrier layer, channel layer, and contact layer, each with optimized thickness and doping. This segmentation allows thicker overall structure for high voltage while maintaining manufacturing control through defined layer specifications.
Solution Approach 2:
The patent transitions from lateral device geometry to vertical device architecture, stacking multiple functional layers vertically. This dimensional change enables thicker GaN layers for high voltage operation while maintaining compact device footprint and manageable manufacturing complexity through vertical epitaxial growth.
3Power
If vertical device structure is implemented, then power density and voltage operation improve, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates sacrificial layers during the epitaxial growth process that are removed later to define contact holes and alignment features. This preliminary action establishes precise alignment references before final metal deposition, ensuring accurate layer alignment in the vertical structure without requiring post-growth alignment operations.
4Reliability
If Schottky metal gates are used, then electron mobility and performance improve, but manufacturing process complexity increases
Solution Approach 1:
The patent replaces semiconductor-based gate structures with Schottky metal gates, substituting the mechanical/structural complexity of doped semiconductor regions with simpler metal deposition. This achieves superior electron mobility and gate control while reducing manufacturing complexity through straightforward metal layer deposition processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in devices capable of operating at higher voltages with greater power density and lower capacitance, offering superior electron mobility, thermal conductivity, and reliability compared to conventional techniques, with the ability to design both normally-off and normally-on functionality.
Implementation Method 1
patterning the plurality of sacrificial layers to provide an etch mask coupled to the second n-type GaN epitaxial layer, forming a self-aligned channel region
Implementation Method 2
forming one or more Schottky metal structures coupled to the self-aligned channel region
Implementation Method 3
forming a first n-type GaN epitaxial layer coupled to the GaN substrate, a second n-type GaN epitaxial layer coupled to the first n-type GaN epitaxial layer, and a third n-type GaN epitaxial layer coupled to the second n-type GaN epitaxial layer
Data Source
AI summary
A semiconductor structure includes a III-nitride substrate and a drift region coupled to the III-nitride substrate along a growth direction. The semiconductor substrate also includes a channel region coupled to the drift region. The channel region is defined by a channel sidewall disposed substantially along the growth direction. The semiconductor substrate further includes a gate region disposed laterally with respect to the channel region.