GaN Voltage Regulator on Silicon Substrate
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Solution Overview
Problem
Silicon-based voltage regulators face inefficiencies at higher voltages, and integrating gallium nitride (GaN) p-type and n-type metal oxide semiconductor (MOS) transistors with silicon substrates is challenging due to lattice mismatch and thermal expansion coefficient differences, leading to defects and surface cracks.
Innovation Solution
Co-integrating GaN p-type and n-type MOS transistors on a silicon substrate using shallow trench isolation structures and polarization layers to form complementary metal oxide semiconductor (CMOS) transistors, leveraging the properties of GaN for high voltage and frequency applications, and utilizing magnesium doping for improved p-channel performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If silicon-based voltage regulators are used, then manufacturing is straightforward and cost-effective, but efficiency deteriorates at higher voltages
Solution Approach 1:
The patent changes the material parameter from silicon to gallium nitride (GaN), which has superior electrical properties for high voltage operation. This material substitution enables the voltage regulator to maintain high efficiency at higher voltages where silicon-based regulators fail, directly addressing the efficiency deterioration problem.
2Reliability
If GaN transistors are integrated on silicon substrate, then high voltage performance is improved, but lattice mismatch and thermal expansion differences cause defects and surface cracks
Solution Approach 1:
The patent introduces an intermediary layer structure between the GaN transistor layer and the silicon substrate. This intermediate layer acts as a buffer to accommodate the lattice mismatch and thermal expansion coefficient differences, preventing defects and surface cracks from forming during the integration process while maintaining high voltage performance.
Solution Approach 2:
The patent creates a composite structure combining GaN material with silicon substrate through carefully engineered intermediate layers. This composite approach leverages the high voltage capabilities of GaN while using silicon's mature manufacturing advantages, and the intermediate layers resolve the material incompatibility issues that would otherwise cause defects.
3Adaptability or versatility
If p-type GaN transistors are fabricated, then complementary CMOS functionality is achieved, but performance gap between p-type and n-type devices exists
Solution Approach 1:
The patent applies local quality enhancement by introducing polarization layers specifically at the p-type GaN transistor regions. These polarization layers create local electric fields that compensate for the inherently lower mobility of holes in p-type GaN, bringing p-type device performance closer to n-type device performance and enabling balanced CMOS functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient voltage regulation and radio frequency power amplification with reduced defects and improved scalability for high-volume manufacturing, bridging the performance gap between p-type and n-type devices by utilizing polarization properties and non-polar GaN growth planes.
Implementation Method 1
a polarization layer on the first gallium nitride layer; a two dimensional electron gas disposed at an interface between the first gallium nitride layer and the polarization layer
Implementation Method 2
utilizing magnesium doping for improved p-channel performance
Data Source
AI summary
A gallium nitride transistor can include a silicon substrate and a first oxide layer and a second oxide layer on the substrate. A first gallium nitride layer may reside on the silicon substrate and the first and second oxide layers. A polarization layer may reside on the first gallium nitride layer. A two dimensional electron gas may exist in the first gallium nitride layer proximate to the polarization layer. A second gallium nitride layer may reside on a first sidewall of the polarization layer and on the first oxide layer on the substrate. A first p-doped gallium nitride layer may reside on the second gallium nitride layer. A third gallium nitride layer may reside on a second sidewall of the polarization layer and on the second oxide layer on the substrate. A second p-doped gallium nitride layer may reside on the second gallium nitride layer.