GaN FET Divided Drain Electrode Parasitic Capacitance
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Solution Overview
Problem
GaN-FETs on Si substrates face challenges with substrate parasitic capacitance and temperature-dependent resistivity, leading to efficiency declines at high temperatures due to the narrow band gap of Si, which limits high-temperature operation and power density.
Innovation Solution
A field-effect transistor design with a divided drain electrode and insulating regions between drain ohmic contacts, reducing parasitic capacitance and thermal resistance by minimizing the drain electrode area and conductive layer under it, while maintaining a large enough gate pitch to prevent channel temperature rise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a high-resistivity Si substrate is used to decrease substrate parasitic capacitance, then parasitic capacitance is reduced, but temperature dependence of resistivity increases causing efficiency decline at high temperatures
Solution Approach 1:
The drain electrode is divided into multiple drain sub-electrodes with insulating regions between them. This segmentation reduces the effective drain electrode area that forms parasitic capacitance with the substrate, while the insulating regions prevent current leakage paths. The segmented structure maintains low parasitic capacitance while allowing the use of lower-resistivity substrates for better thermal stability.
2Ease of manufacture
If Si substrate is used instead of sapphire or SiC, then manufacturing cost is reduced, but substrate parasitic capacitance increases due to lower resistivity
Solution Approach 1:
By segmenting the drain electrode into multiple sub-electrodes separated by insulating regions, the patent reduces the effective area forming parasitic capacitance with the Si substrate. This allows the use of low-cost Si substrates while maintaining low parasitic capacitance characteristics that would otherwise require expensive semi-insulating substrates.
Solution Approach 2:
The insulating regions are introduced to extract or remove the harmful capacitive coupling between the drain electrode and substrate. By taking out the conductive path in portions and replacing it with insulating material, the parasitic capacitance is reduced without changing the substrate material itself.
3Loss of energy
If drain electrode area is minimized to reduce parasitic capacitance, then parasitic capacitance decreases, but thermal resistance increases making it difficult to dissipate heat
Solution Approach 1:
The drain electrode is segmented into multiple sub-electrodes that can be distributed over a larger area. This segmentation allows the electrical active area to be minimized for low capacitance while the physical footprint is expanded for better heat dissipation. The insulating regions between sub-electrodes do not conduct heat, allowing thermal paths to extend laterally.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses parasitic capacitance and temperature dependence of drain efficiency, enabling high-efficiency operation at high temperatures using low-cost Si substrates, thereby achieving high power density and cost reduction.
Implementation Method 1
In order to decrease the substrate parasitic capacitance of a FET for high Radio-frequency (RF) operation
Implementation Method 2
minimizing the drain electrode area and conductive layer under it
Implementation Method 3
maintaining a large enough gate pitch to prevent channel temperature rise
Implementation Method 4
Si has a narrow band gap, the electrons are easily transferred from the valence band to conduction one while the ambient temperature rises, so an intrinsic current flows at a higher temperature
Data Source
AI summary
A field-effect transistor (FET) in which a gate electrode is located between a source electrode formed on one side of the gate electrode and a drain electrode formed on the other side, a source ohmic contact is formed under the source electrode and a drain ohmic contact is formed under the drain electrode. In the FET, the rise in the channel temperature is suppressed, the parasitic capacitance with a substrate is decreased, and the temperature dependence of drain efficiency is reduced, so that highly efficient operation can be achieved at high temperatures. The drain electrode is divided into a plurality of drain sub-electrodes spaced from each other and an insulating region is formed between the drain ohmic contacts formed under the drain sub-electrodes.