Ganged Read Operation for Memory Sub-Blocks
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Solution Overview
Problem
Memory systems face challenges in preventing data loss events due to defects in access lines and read disturb, which can cause threshold voltage distributions to shift, leading to incorrect logic states being stored or read.
Innovation Solution
The memory system performs a ganged read operation on multiple sub-blocks to verify the programming of memory cells by biasing word lines to specific voltages and reading logic states, allowing for the detection of errors and potential data loss events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional read operations are performed on multiple sub-blocks sequentially, then verification of programming is achieved, but the time required for verification is excessive
Solution Approach 1:
The patent combines multiple sub-block reads into a single ganged read operation by connecting multiple bit lines together and reading from multiple sub-blocks simultaneously through a shared sense amplifier, thereby reducing verification time while maintaining accuracy
Solution Approach 2:
The patent applies preliminary actions by pre-charging bit lines and preparing sense amplifiers before the actual read operation, enabling faster simultaneous reading from multiple sub-blocks without compromising verification reliability
2Quantity of substance
If data is stored in memory cells, then information is retained, but data loss events occur due to defects in access lines and read disturb causing threshold voltage shifts
Solution Approach 1:
The patent implements feedback by performing verification reads after write operations to detect threshold voltage shifts and data integrity issues, then using this information to refresh or correct data before it is lost
Solution Approach 2:
The patent applies preliminary verification actions by reading back programmed data immediately after write operations to detect potential data loss events before they occur, enabling preventive data refresh
Data Source
AI summary
Methods, systems, and devices for a ganged read operation for multiple sub-blocks are described. The method may include writing a respective first logic state to each memory cell of a set of memory portions and biasing a first word line and a second word line to a first voltage. In some examples, the first word line may correspond to a first memory portion and the second word line may correspond to a second memory portion. Further, the method may include applying a first read pulse to the first word line and a second read pulse to the second word line and reading a second logic state from one or more memory cells of the first memory portion and the second memory portion. Further, the method may include validating the write operation based on reading the second logic state from the memory cells of the first memory portion and the second memory portion.