Multi-Layer Gap-Fill Dielectrics for CTE-Matched Die Structures
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the warping and stress induction due to coefficient of thermal expansion (CTE) mismatch between integrated circuit dies and the gap-fill dielectrics, which affects the reliability and yield of the die structure.
Innovation Solution
Incorporating an inner gap-fill dielectric with a higher CTE than the outer gap-fill dielectric, matched to the CTE of the integrated circuit dies, to mitigate CTE mismatch and reduce warping and stress, using materials like silicon oxynitride or transition metal oxides to enhance compressive strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-layer gap-fill dielectric is used, then the manufacturing process is simple, but CTE mismatch causes warping and stress in the die structure
Solution Approach 1:
The gap-fill dielectric is divided into multiple layers with different CTE values. The first layer has a CTE matched to the integrated circuit dies, while the second layer has a different CTE. This segmentation allows each layer to handle different stress conditions, preventing warping and improving die structure stability without significantly complicating the manufacturing process.
2Reliability
If the gap-fill dielectric CTE is matched to the integrated circuit die CTE, then warping is reduced, but material selection becomes more restricted
Solution Approach 1:
By segmenting the gap-fill dielectric into multiple layers, the invention allows different materials to be used in each layer. The first layer uses a material with CTE matched to the integrated circuit die for warping resistance, while the second layer can use a different material optimized for other properties such as stress management or manufacturing compatibility, thus expanding material selection flexibility.
Solution Approach 2:
The invention changes the CTE parameter distribution across multiple layers rather than requiring a single material to satisfy all CTE requirements. This allows optimization of each layer's CTE independently, enabling better warping resistance in the first layer while maintaining versatility in material selection for the second layer.
3Reliability
If multiple gap-fill dielectric layers are used, then CTE mismatch and warping are mitigated, but the manufacturing process becomes more complex
Solution Approach 1:
The gap-fill dielectric is segmented into two functional layers: a first layer with CTE matched to the integrated circuit die for stress resistance, and a second layer with different CTE for complementary performance. This segmentation mitigates warping and improves stress resistance while keeping the manufacturing process complexity manageable through a systematic multi-layer approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces CTE mismatch and warping, enhancing the reliability and yield of the die structure by providing better stress resistance and structural integrity.
Implementation Method 1
the inner gap-fill dielectric has a higher CTE than the outer gap-fill dielectric. The CTE of the inner gap-fill dielectric may be matched to the CTE of the integrated circuit dies, which can reduce a CTE mismatch in the die structure
Data Source
AI summary
Gap-fill dielectrics for die structures and methods of forming the same are provided. In an embodiment, a device includes: an outer gap-fill dielectric having a first coefficient of thermal expansion; a first integrated circuit die in the outer gap-fill dielectric; a second integrated circuit die in the outer gap-fill dielectric; an inner gap-fill dielectric between the first integrated circuit die and the second integrated circuit die, the inner gap-fill dielectric having a second coefficient of thermal expansion, the second coefficient of thermal expansion being greater than the first coefficient of thermal expansion; and a third integrated circuit die over the inner gap-fill dielectric, the third integrated circuit die bonded to the first integrated circuit die and to the second integrated circuit die.