Gap Fill Profile Control for Lower Gate Fringing Capacitance
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Solution Overview
Problem
The scaling down of semiconductor devices increases complexity and results in undesirable parasitic capacitances and fringing capacitances due to the gap fill structure between gate structures and active regions, which slow down integrated circuits and impact threshold voltage.
Innovation Solution
A method is introduced to mitigate fringing capacitances by controlling the profile of the gap fill structure, with a first portion in the gate structure and a second portion in the interlayer dielectric structure, by increasing the width of the first portion and decreasing the dimensions of the second portion to reduce the effective dielectric constant, using different etching rates and materials like silicon nitride and silicon oxide.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gap fill structure is used to separate gate structures, then manufacturing feasibility is improved, but parasitic capacitances and fringing capacitances increase
Solution Approach 1:
The gap fill structure is designed with different dielectric materials in different regions: a first gap fill structure with higher dielectric constant is positioned closer to the gate structure where field control is most critical, while a second gap fill structure with lower dielectric constant is positioned farther away. This local differentiation reduces fringing capacitance while maintaining manufacturing feasibility.
Solution Approach 2:
The patent employs composite dielectric structures combining multiple materials with different dielectric constants. The first gap fill structure (e.g., silicon nitride with k≈7.5) and second gap fill structure (e.g., silicon oxide with k≈3.9) work together to optimize electrical performance while maintaining structural integrity and manufacturability.
2Productivity
If device dimensions are scaled down, then storage capacity and processing speed are improved, but manufacturing complexity increases
Solution Approach 1:
The gap fill structure is segmented into distinct portions: a first gap fill structure and a second gap fill structure with different materials and positions. This segmentation allows independent optimization of each region's electrical characteristics while maintaining overall manufacturing feasibility through standardized fabrication processes.
Solution Approach 2:
The patent optimizes multiple parameters including the dielectric constants of different materials, the dimensions and positions of gap fill structures, and the spacing between gate structures. By carefully adjusting these parameters, the design achieves high storage capacity while managing manufacturing complexity through systematic parameter optimization.
3Speed
If fringing capacitance is reduced by decreasing distance between gate structures and active regions, then circuit speed is improved, but manufacturing precision requirements increase
Solution Approach 1:
The dielectric material properties are locally optimized: higher dielectric constant materials are used closer to gate structures where field confinement is most effective, gradually transitioning to lower dielectric constant materials farther away. This local quality gradient reduces fringing capacitance while providing manufacturing tolerance buffer zones.
Solution Approach 2:
Composite dielectric structures with graded dielectric constants are employed to reduce fringing capacitance. The combination of materials with different electrical properties creates field distribution patterns that minimize parasitic effects while maintaining robustness against manufacturing variations through material property diversity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces fringing capacitance by decreasing the distance between gate structures and active regions, improving the performance of integrated circuits by reducing parasitic capacitances and threshold voltage shifts.
Implementation Method 1
using different etching rates and materials like silicon nitride and silicon oxide
Data Source
AI summary
The present disclosure describes a method of fabricating a semiconductor structure that includes forming a gate structure over a substrate, forming an interlayer dielectric structure surrounding the gate structures, and forming a first opening in the gate structure and the interlayer dielectric structure. The first opening has a first portion in the gate structure and a second portion in the interlayer dielectric structure, in which the first portion has a width larger than the second portion. The method further includes depositing a dielectric layer in the first opening and forming a second opening over the first opening. The first portion of the opening remains open and the second portion of the opening is filled after depositing the dielectric layer. The second opening in the gate structure has a depth larger than the first opening in the gate structure.