3D Semiconductor Memory Structure Using Gapfill Contacts for Dense Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing two-dimensional semiconductor devices face limitations in integration due to the high cost of fine pattern forming technology, which restricts their ability to increase data storage capacity and reduce production costs.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a peripheral circuit structure on a first substrate and a cell array structure on the peripheral circuit structure, featuring stacked gate electrodes, insulating layers, and conductive patterns to enhance integration and electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration is greatly influenced by fine pattern forming technology cost and cannot achieve high data storage capacity
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional semiconductor memory devices by stacking multiple memory cell layers vertically. This dimensional change allows data storage capacity to increase significantly without requiring finer pattern formation, thereby avoiding the cost constraints of advanced lithography while achieving high integration.
2Quantity of substance
If fine pattern forming technology is advanced to increase integration, then data storage capacity increases, but manufacturing cost becomes extremely expensive
Solution Approach 1:
By moving to three-dimensional stacking architecture, the patent achieves high data storage capacity without relying on costly fine pattern forming technology. The vertical stacking allows multiple memory cells to be integrated using relatively coarser patterning processes, significantly reducing manufacturing costs compared to achieving similar capacity through two-dimensional scaling.
Solution Approach 2:
The three-dimensional memory device is divided into multiple stacked memory cell layers, each layer being a separate segment. This segmentation allows each layer to be fabricated using standard patterning processes, avoiding the need for extremely fine single-layer patterning, thereby reducing overall manufacturing cost while achieving high total capacity.
3Quantity of substance
If three-dimensional semiconductor memory devices are implemented, then data storage capacity and integration are improved, but device structure becomes more complex
Solution Approach 1:
The three-dimensional memory device is segmented into multiple identical or similar memory cell layers stacked vertically. Each layer has a relatively simple structure that can be fabricated using standard processes. The overall device complexity is managed by repeating this simple unit structure multiple times rather than creating a single complex two-dimensional layout.
Solution Approach 2:
The stacked memory cell layers use uniform structures and materials throughout the stack, allowing the same fabrication processes and design rules to be applied to each layer. This universality simplifies the overall device design and manufacturing, reducing the complexity that would otherwise arise from having to design and fabricate different structures for different regions.
Data Source
AI summary
A three-dimensional semiconductor memory device may include a peripheral structure and a cell structure on the peripheral structure. The cell structure may include a substrate having first and second surfaces, which are opposite to each other, a stack including gate electrodes, which are stacked on the first surface of the substrate, an insulating layer on the second surface of the substrate, a penetration contact plug penetrating the first surface of the substrate, a first gapfill conductive pattern provided to penetrate the second surface of the substrate and the insulating layer and spaced apart from the penetration contact plug, a second gapfill conductive pattern provided to penetrate the second surface of the substrate and the insulating layer and connected to the penetration contact plug, a first gapfill spacer between the first gapfill conductive pattern and the substrate, and a second gapfill spacer between the second gapfill conductive pattern and the substrate.